ADS54J42 Datasheet, PDF (61/81 Pages) Texas Instruments – Dual-Channel, 14-Bit, 625-MSPS, Analog-to-Digital Converter

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8.5.3.5.4 Register 3h (address = 3h), JESD Digital Page (6900h)
ADS54J42
SBAS756A – FEBRUARY 2016 – REVISED MARCH 2016
Figure 116. Register 3h
7
6
5
4
3
FORCE LMFC COUNT
LMFC COUNT INIT
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
2
1
0
RELEASE ILANE SEQ
R/W-0h
Table 54. Register 3h Field Descriptions
Bit Field
7 FORCE LMFC COUNT
6-2 MASK SYSREF
1-0 RELEASE ILANE SEQ
Type
R/W
R/W
R/W
Reset
0h
0h
0h
Description
This bit forces the LMFC count.
0 = Normal operation
1 = Enables using a different starting value for the LMFC counter
When SYSREF transmits to the digital block, the LMFC count resets to
0 and K28.5 stops transmitting when the LMFC count reaches 31. The
initial value that the LMFC count resets to can be set using LMFC
COUNT INIT. In this manner, the receiver can be synchronized early
because the LANE ALIGNMENT SEQUENCE is received early. The
FORCE LMFC COUNT register bit must be enabled.
These bits delay the generation of the lane alignment sequence by 0, 1,
2, or 3 multi-frames after the code group synchronization.
00 = 0
01 = 1
10 = 2
11 = 3
8.5.3.5.5 Register 5h (address = 5h), JESD Digital Page (6900h)
Figure 117. Register 5h
7
6
5
4
SCRAMBLE EN
0
0
0
R/W-Undefined
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
3
0
W-0h
2
0
W-0h
1
0
W-0h
0
0
W-0h
Bit Field
7
SCRAMBLE EN
6-0 0
Table 55. Register 5h Field Descriptions
Type
R/W
W
Reset
Undefined
0h
Description
This bit is the scramble enable bit in the JESD204B interface.
0 = Scrambling disabled
1 = Scrambling enabled
Must write 0
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