ADS54J42 Datasheet, PDF (1/81 Pages) Texas Instruments – Dual-Channel, 14-Bit, 625-MSPS, Analog-to-Digital Converter

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ADS54J42
SBAS756A – FEBRUARY 2016 – REVISED MARCH 2016
ADS54J42
Dual-Channel, 14-Bit, 625-MSPS, Analog-to-Digital Converter
1 Features
•1 14-Bit Resolution, Dual-Chanel, 625-MSPS ADC
• Noise Floor: –157 dBFS/Hz
• Spectral Performance (f_IN = 170 MHz at –1 dBFS):
– SNR: 71.0 dBFS
– NSD: –155.9 dBFS/Hz
– SFDR: 85 dBc
– SFDR: 93 dBc (Except HD2, HD3, and
Interleaving Tones)
• Spectral Performance (f_IN = 350 MHz at –1 dBFS):
– SNR: 69 dBFS
– NSD: –153.9 dBFS/Hz
– SFDR: 76 dBc
– SFDR: 90 dBc (Except HD2, HD3, and
Interleaving Tones)
• Channel Isolation: 100 dBc at f_IN = 170 MHz
• Input Full-Scale: 1.9 V_PP
• Input Bandwidth (3 dB): 1.2 GHz
• On-Chip Dither
• Integrated Wideband DDC Block
• JESD204B Interface with Subclass 1 Support:
– 2 Lanes per ADC at 6.25 Gbps
– 4 Lanes per ADC at 3.125 Gbps
– Support for Multi-Chip Synchronization
• Power Dissipation: 970 mW/Ch at 625 MSPS
• Package: 72-Pin VQFNP (10 mm × 10 mm)
2 Applications
• Radar and Antenna Arrays
• Broadband Wireless
• Cable CMTS, DOCSIS 3.1 Receivers
• Communications Test Equipment
• Microwave Receivers
• Software Defined Radio (SDR)
• Digitizers
• Medical Imaging and Diagnostics
3 Description
The ADS54J42 is a low-power, wide-bandwidth, 14-
bit, 625-MSPS, dual-channel, analog-to-digital
converter (ADC). Designed for high signal-to-noise
ratio (SNR), the device delivers a noise floor of
–157 dBFS/Hz for applications aiming for highest
dynamic range over a wide instantaneous bandwidth.
The device supports the JESD204B serial interface
with data rates up to 6.25 Gbps. The buffered analog
input provides uniform input impedance across a wide
frequency range and minimizes sample-and-hold
glitch energy. Each ADC channel optionally can be
connected to a wideband digital down-converter
(DDC) block. The ADS54J42 provides excellent
spurious-free dynamic range (SFDR) over a large
input frequency range with very low power
consumption.
The JESD204B interface reduces the number of
interface lines, allowing high system integration
density. An internal phase-locked loop (PLL)
multiplies the ADC sampling clock to derive the bit
clock that is used to serialize the 14-bit data from
each channel.
PART NUMBER
ADS54J42
Device Information
PACKAGE
BODY SIZE (NOM)
VQFNP (72)
10.00 mm × 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
FFT for 170-MHz Input Signal
0
SNR = 71 dBFS
SFDR = 85 dBc
-20 _{Non HD2,HD3 Spur = 93 dBc}
-40
-60
-80
-100
-120
0
62.5
125
187.5
250
Input Frequency (MHz)
312.5
D101
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.