ADC12J4000 Datasheet, PDF (61/94 Pages) Texas Instruments – 12-Bit 4 GSPS ADC With Integrated DDC

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7.6.1.4 Clock (0x030 to 0x03F)
Address
0x030
0x031
0x032
0x033
0x034
0x035
0x036
0x037
0x038-0x03F
Reset
0xC0
0x07
0x80
0xC3
0x2F
0xDF
0x00
0x45
Undefined
Acronym
CLKGEN_0
CLKGEN_1
CLKGEN_2
ANA_MISC
IN_CL_EN
RESERVED
RESERVED
RESERVED
RESERVED
ADC12J4000
SLAS989C – JANUARY 2014 – REVISED JULY 2015
Table 55. Clock Registers
Register Name
Clock Generator Control 0 Register
Clock Generator Status Register
Clock Generator Control 2 Register
Analog Miscellaneous Register
Clamp Enable Register
RESERVED
RESERVED
RESERVED
RESERVED
Section
Go
Go
Go
Go
Go
7.6.1.4.1 Clock Generator Control 0 Register (address = 0x030) [reset = 0xC0]
Figure 66. Clock Generator Control 0 Register (CLKGEN_0)
7
SysRef_Rcvr_E
n
R/W-1
6
SysRef_Pr_En
R/W-1
5
SysRefDetClr
R/W-0
4
Clear Dirty
Capture
R/W-0
3
RESERVED
R/W-0
2
1
0
DC_LVPECL_C DC_LVPECL_S DC_LVPECL_T
LK_en
YSREF_en
S_en
R/W-0
R/W-0
R/W-0
Table 56. CLKGEN_0 Field Descriptions
Bit Field
7
SysRef_Rcvr_En
6
SysRef_Pr_En
5
SysRefDetClr
4
Clear Dirty Capture
3
RESERVED
2
DC_LVPECL_CLK_en
1
DC_LVPECL_SYSREF_en
0
DC_LVPECL_TS_en
Type
R/W
Reset
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Default: 1
0 : SYSREF receiver is disabled.
1 : SYSREF receiver is enabled (default)
To power down the SYSREF receiver, clear this bit first, then
clear SysRef_Rcvr_En. To power up the SYSREF receiver, set
SysRef_Rcvr_En first, then set this bit.
Default: 1
0 : SYSREF Processor is disabled.
1 : SYSREF Processor is enabled (default)
Default: 0
Write a 1 and then a 0 to clear the SysRefDet status bit.
Default: 0
Write a 1 and then a 0 to clear the DC status bit.
Default: 0
Default: 0
Set this bit if DEVCLK is a DC-coupled LVPECL signal through
a 50-Ω resistor.
Default: 0
Set this bit if SYSREF is a DC-coupled LVPECL signal through
a 50-Ω resistor.
Default: 0
Set this bit if TimeStamp is a DC-coupled LVPECL signal
through a 50-Ω resistor.
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