English
Language : 

ADC12J4000 Datasheet, PDF (18/94 Pages) Texas Instruments – 12-Bit 4 GSPS ADC With Integrated DDC
◁
ADC12J4000
SLAS989C – JANUARY 2014 – REVISED JULY 2015
www.ti.com
6.9 Typical Characteristics
Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN FSR (AC coupled) =
Default setting, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 4 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3
kΩ ±0.1%, after a Foreground mode calibration with Timing Calibration enabled. TA = 25°C. VI = –1 dBFS.
80
SNR (dBFS)
75
SINAD (dBFS)
SFDR (dBFS)
70
65
60
55
50
45
0 300 600 900 1200 1500 1800 2100 2400 2700 3000
Input Frequency (MHz)
D002
DDC bypass mode
Sampling rate = 4000 MSPS
Figure 3. SNR, SINAD, SFDR vs Input Frequency
100
SNR (dBFS)
SINAD (dBFS)
90
SFDR (dBFS)
80
80
SNR (dBFS)
75
SINAD (dBFS)
SFDR (dBFS)
70
65
60
55
50
45
1200 1600 2000 2400 2800 3200 3600 4000 4400 4800 5200
Sampling Rate (MSPS)
D001
DDC bypass mode
FIN = 608 MHz
Figure 4. SNR, SINAD, SFDR vs Sampling rate
100
SNR (dBFS)
SINAD (dBFS)
90
SFDR (dBFS)
80
70
70
60
60
50
50
40
0
4
8
DDC bypass mode
12 16 20
Decimation Factor
24 28 32
D011
FIN = 608 MHz
Figure 5. SNR, SINAD, SFDR vs Decimation Setting
80
SNR (dBFS)
75
SINAD (dBFS)
SFDR (dBFS)
70
65
60
55
50
45
-10
-5
0
5
10
All Supply Voltage Variation from Nominal (%)
D027
DDC bypass mode
FIN = 608 MHz
Figure 7. SNR, SINAD, SFDR vs Supply Voltage
40
0
4
8
DDC bypass mode
12 16 20
Decimation Factor
24 28 32
D016
FIN = 2483 MHz
Figure 6. SNR, SINAD, SFDR vs Decimation Setting
80
SNR (dBFS)
75
SINAD (dBFS)
SFDR (dBFS)
70
65
60
55
50
45
-50
-25
0
25
50
Ambient Temperature (°C)
DDC bypass mode
75
100
D030
FIN = 608 MHz
Figure 8. SNR, SINAD, SFDR vs Temperature
18
Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated
Product Folder Links: ADC12J4000
 ▷