ADC10D1000 Datasheet, PDF (61/82 Pages) National Semiconductor (TI) – Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS ADC

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ADC10D1000, ADC10D1500
SNAS462Q – OCTOBER 2008 – REVISED MARCH 2013
C_couple
C_couple
V_IN+
V_IN-
V_CMO
ADC10D1000
Figure 71. AC-coupled Differential Input
The analog inputs for the ADC10D1000/1500 are internally buffered, which simplifies the task of driving these
inputs and the RC pole which is generally used at sampling ADC inputs is not required. If the user desires to
place an amplifier circuit before the ADC, care should be taken to choose an amplifier with adequate noise and
distortion performance, and adequate gain at the frequencies used for the application.
DC-coupled Input Signals
In DC-coupled Mode, the ADC10D1000/1500 differential inputs must have the correct common-mode voltage.
This voltage is provided by the device itself at the V_CMO output pin. It is recommended to use this voltage
because the V_CMO output potential will change with temperature and the common-mode voltage of the driving
device should track this change. Full-scale distortion performance falls off as the input common mode voltage
deviates from V_CMO. Therefore, it is recommended to keep the input common-mode voltage within 100 mV of
V_CMO (typical), although this range may be extended to ±150 mV (maximum). See V_CMI in Converter Electrical
Characteristics – Analog Input/Output and Reference Characteristics and ENOB vs. V_CMI in Typical Performance
Plots . Performance in AC- and DC-coupled Mode are similar, provided that the input common mode voltage at
both analog inputs remains within 100 mV of V_CMO.
Single-Ended Input Signals
The analog inputs of the ADC10D1000/1500 are not designed to accept single-ended signals. The best way to
handle single-ended signals is to first convert them to differential signals before presenting them to the ADC. The
easiest way to accomplish single-ended to differential signal conversion is with an appropriate balun-transformer,
as shown in Figure 72.
50:
Source
1:2 Balun
C_{couple VIN+}
100:
C_couple ^VIN-
ADC10D1000
Figure 72. Single-Ended to Differential Conversion Using a Balun
When selecting a balun, it is important to understand the input architecture of the ADC. The impedance of the
analog source should be matched to the ADC10D1000/1500's on-chip 100Ω differential input termination resistor.
The range of this termination resistor is specified as R_IN in Converter Electrical Characteristics – Analog
Input/Output and Reference Characteristics.
THE CLOCK INPUTS
The ADC10D1000/1500 has a differential clock input, CLK+ and CLK-, which must be driven with an AC-
coupled, differential clock signal. This provides the level shifting to the clock to be driven with LVDS, PECL,
LVPECL, or CML levels. The clock inputs are internally terminated to 100Ω differential and self-biased. This
section covers coupling, frequency range, level, duty-cycle, jitter, and layout considerations.
CLK Coupling
The clock inputs of the ADC10D1000/1500 must be capacitively coupled to the clock pins as indicated in
Figure 73.
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