ADC10D1000 Datasheet, PDF (18/82 Pages) National Semiconductor (TI) – Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS ADC

ADC10D1000, ADC10D1500
SNAS462Q – OCTOBER 2008 – REVISED MARCH 2013
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Converter Electrical Characteristics – Dynamic Converter Characteristics (continued)
The following specifications apply after calibration for V_A = V_DR = V_TC = V_E = +1.9V; I- and Q-channels, AC-coupled, unused
channel terminated to AC ground, FSR Pin = High; C_L = 10 pF; Differential, AC coupled Sine Wave Sampling Clock, f_CLK =
1.0/1.5 GHz at 0.5 V_P-P with 50% duty cycle (as specified); V_BG = Floating; Non-Extended Control Mode; Rext = Rtrim =
3300Ω ± 0.1%; Analog Signal Source Impedance = 100Ω Differential; 1:2 Demultiplex Non-DES Mode; Duty Cycle Stabilizer
on. Boldface limits apply for T_A = T_MIN to T_MAX. All other limits T_A = 25°C, unless otherwise noted. ^{(1) (2) (3) (4)}
_
Symbol
Parameter
Conditions
ADC10D1000
Typ
Lim
ADC10D1500
Typ Lim
Units
(Limits)
3rd Harm
Third Harmonic Distortion
A_IN = 100 MHz @ -0.5 dBFS
-69
-67
dBc
A_IN = 248 MHz @ -0.5 dBFS
-65
-70
dBc
A_IN = 373 MHz @ -0.5 dBFS
-62
dBc
A_IN = 498 MHz @ -0.5 dBFS
-63
dBc
A_IN = 748 MHz @ -0.5 dBFS
-62
dBc
SFDR
Spurious-Free Dynamic Range A_IN = 100 MHz @ -0.5 dBFS
59.3
67
dBc
A_IN = 248 MHz @ -0.5 dBFS
58.9
62
dBc
A_IN = 373 MHz @ -0.5 dBFS
60
dBc
A_IN = 498 MHz @ -0.5 dBFS
57.4
dBc
A_IN = 748 MHz @ -0.5 dBFS
59
dBc
18
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