ADC10D1000 Datasheet, PDF (1/82 Pages) National Semiconductor (TI) – Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS ADC

ADC10D1000, ADC10D1500
www.ti.com
SNAS462Q – OCTOBER 2008 – REVISED MARCH 2013
ADC10D1000/ADC10D1500 Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS
ADC
Check for Samples: ADC10D1000, ADC10D1500
FEATURES
1
•2 Excellent Accuracy and Dynamic Performance
• Pin Compatible with ADC12D1000/1600/1800
• Low Power Consumption, Further Reduced at
Lower Fs
• Internally Terminated, Buffered, Differential
Analog Inputs
• R/W SPI Interface for Extended Control Mode
• Dual-Edge Sampling Mode, in Which the I- and
Q-channels Sample One Input at Twice the
Sampling Clock Rate
• Test Patterns at Output for System Debug
• Programmable 15-bit Gain and 12-bit Plus Sign
Offset
• Programmable t_AD Adjust Feature
• 1:1 Non-demuxed or 1:2 Demuxed LVDS
Outputs
• AutoSync Feature for Multi-Chip Systems
• Single 1.9V ± 0.1V Power Supply
• 292-Ball BGA Package (27mm x 27mm x
2.4mm with 1.27mm Ball-Pitch); No Heat Sink
Required
APPLICATIONS
• Wideband Communications
• Data Acquisition Systems
• Digital Oscilloscopes
DESCRIPTION
The ADC10D1000/1500 is the latest advance in TI's
Ultra-High-Speed ADC family. This low-power, high-
performance CMOS analog-to-digital converter
digitizes signals at 10-bit resolution for dual channels
at sampling rates of up to 1.0/1.5 GSPS (Non-DES
Mode) or for a single channel up to 2.0/3.0 GSPS
(DES Mode). The ADC10D1000/1500 achieves
excellent accuracy and dynamic performance while
dissipating less than 2.8/3.6 Watts. The product is
packaged in a leaded or lead-free 292-ball thermally
enhanced BGA package over the rated industrial
temperature range of -40°C to +85°C.
The ADC10D1000/1500 builds upon the features,
architecture and functionality of the 8-bit GHz family
of ADCs. An expanded feature set includes AutoSync
for multi-chip synchronization, 15-bit programmable
gain and 12-bit plus sign programmable offset
adjustment for each channel. The improved internal
track-and-hold amplifier and the extended self-
calibration scheme enable a very flat response of all
dynamic parameters beyond Nyquist, producing
9.1/9.0 Effective Number of Bits (ENOB) with a 100
MHz input signal and a 1.0/1.5 GHz sample rate
while providing a 10^-18 Code Error Rate (CER)
Dissipating a typical 2.77/3.59 Watts in Non-
Demultiplex Mode at 1.0/1.5 GSPS from a single
1.9V supply, this device is specified to have no
missing codes over the full operating temperature
range.
Each channel has its own independent DDR Data
Clock, DCLKI and DCLKQ, which are in phase when
both channels are powered up, so that only one Data
Clock could be used to capture all data, which is sent
out at the same rate as the input sample clock. If the
1:2 Demux Mode is selected, a second 10-bit LVDS
bus becomes active for each channel, such that the
output data rate is sent out two times slower to relax
data-capture timing requirements. The part can also
be used as a single 2.0/3.0 GSPS ADC to sample
one of the I or Q inputs. The output formatting can be
programmed to be offset binary or two's complement
and the Low Voltage Differential Signaling (LVDS)
digital outputs are compatible with IEEE 1596.3-1996,
with the exception of an adjustable common mode
voltage between 0.8V and 1.2V to allow for power
reduction for well-controlled back planes.
1
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2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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