TMS320UC5402_09 Datasheet, PDF (60/77 Pages) Texas Instruments – Digital Signal Processor

Electrical Specifications
4.12 Multichannel Buffered Serial Port (McBSP) Timing
4.12.1 McBSP Transmit and Receive Timings
Table 4−18 and Table 4−19 assume testing over recommended operating conditions and H = 0.5t_c(CO) (see
Figure 4−20 and Figure 4−21).
Table 4−18. McBSP Transmit and Receive Timing Requirements^†
MIN MAX UNIT
tc(BCKRX)
tw(BCKRX)
Cycle time, BCLKR/X
Pulse duration, BCLKR/X high or BCLKR/X low
tsu(BFRH-BCKRL) Setup time, external BFSR high before BCLKR low
BCLKR/X ext
4H
ns
BCLKR/X ext 2H−1
ns
BCLKR int
20
ns
BCLKR ext
0
th(BCKRL-BFRH) Hold time, external BFSR high after BCLKR low
BCLKR int
−3
ns
BCLKR ext
4
tsu(BDRV-BCKRL) Setup time, BDR valid before BCLKR low
BCLKR int
17
ns
BCLKR ext
0
th(BCKRL-BDRV) Hold time, BDR valid after BCLKR low
BCLKR int
0
ns
BCLKR ext
8
tsu(BFXH-BCKXL) Setup time, external BFSX high before BCLKX low
BCLKX int
20
ns
BCLKX ext
0
th(BCKXL-BFXH) Hold time, external BFSX high after BCLKX low
BCLKX int
−4
ns
BCLKX ext
5
tr(BCKRX)
Rise time, BCLKR/X
BCLKR/X ext
8 ns
tf(BCKRX)
Fall time, BCLKR/X
BCLKR/X ext
8 ns
† _{CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.}
50 SPRS096C
April 1999 − Revised October 2008