TMS320UC5402_09 Datasheet, PDF (48/77 Pages) Texas Instruments – Digital Signal Processor

Electrical Specifications
4.6.2 Memory Write
Table 4−7 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5t_c(CO) (see
Figure 4−6).
Table 4−7. Memory Write Switching Characteristics^†
PARAMETER
td(CLKH-A)
td(CLKL-A)
td(CLKL-MSL)
Delay time, CLKOUT high to address valid‡
Delay time, CLKOUT low to address valid§
Delay time, CLKOUT low to MSTRB low
td(CLKL-D)W
Delay time, CLKOUT low to data valid
td(CLKL-MSH)
Delay time, CLKOUT low to MSTRB high
td(CLKH-RWL)
Delay time, CLKOUT high to R/W low
td(CLKH-RWH)
Delay time, CLKOUT high to R/W high
td(RWL-MSTRBL) Delay time, R/W low to MSTRB low
th(A)W
Hold time, address valid after CLKOUT high‡
th(D)MSH
Hold time, write data valid after MSTRB high
tw(SL)MS
tsu(A)W
Pulse duration, MSTRB low
Setup time, address valid before MSTRB low
tsu(D)MSH
Setup time, write data valid before MSTRB high
ten(D−RWL)
Enable time, data bus driven after R/W low
tdis(RWH−D)
Disable time, R/W high to data bus high impedance
† _{Address, PS, and DS timings are all included in timings referenced as address.}
‡ _{In the case of a memory write preceded by a memory write}
§ _{In the case of a memory write preceded by an I/O cycle}
MIN MAX
0
5
0
8
0
8
0
17
0
8
−1
5
−2
5
H−4 H+2
0
5
H−3 H+14
2H−5
2H−4
2H−14 2H+5
H−5
0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
38 SPRS096C
April 1999 − Revised October 2008