TMS320UC5402_09 Datasheet, PDF (38/77 Pages) Texas Instruments – Digital Signal Processor

Functional Overview
2.4.1 IFR and IMR Registers
The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in
Figure 2−10.
15−14
RES
13
DMAC5
12
DMAC4
11
10
9
BXINT1
or
DMAC3
BRINT1
or
DMAC2
HPINT
8
INT3
7
TINT1
or
DMAC1
6
RES
or
DMAC0
5
4
BXINT0 BRINT0
3
TINT0
Figure 2−10. IFR and IMR Registers
2
1
0
INT2 INT1 INT0
NUMBER
15−14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 2−14. IFR and IMR Register Bit Fields
BIT
NAME
−
DMAC5
DMAC4
BXINT1/DMAC3
BRINT1/DMAC2
HPINT
INT3
TINT1/DMAC1
Reserved or DMAC0
BXINT0
BRINT0
TINT0
INT2
INT1
INT0
FUNCTION
Reserved for future expansion
DMA channel 5 interrupt flag/mask bit
DMA channel 4 interrupt flag/mask bit
This bit can be configured as either the McBSP1 transmit interrupt flag/mask bit, or the DMA
channel 3 interrupt flag/mask bit. The selection is made in the DMPREC register.
This bit can be configured as either the McBSP1 receive interrupt flag/mask bit, or the DMA
channel 2 interrupt flag/mask bit. The selection is made in the DMPREC register.
Host to C54x interrupt flag/mask
External interrupt 3 flag/mask
This bit can be configured as either the timer1 interrupt flag/mask bit, or the DMA channel 1
interrupt flag/mask bit. The selection is made in the DMPREC register.
This bit can be configured either as reserved or as the DMA channel 0 interrupt flag/mask bit. The
selection is made in the DMPREC register.
McBSP0 transmit interrupt flag/mask bit
McBSP0 receive interrupt flag/mask bit
Timer 0 interrupt flag/mask bit
External interrupt 2 flag/mask bit
External interrupt 1 flag/mask bit
External interrupt 0 flag/mask bit
28 SPRS096C
April 1999 − Revised October 2008