TMS320F2810_12 Datasheet, PDF (6/172 Pages) Texas Instruments – Digital Signal Processors

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
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6-21 EVBSOC Timing ................................................................................................................ 113
6-22 External Interrupt Timing....................................................................................................... 114
6-23 General-Purpose Output Timing .............................................................................................. 115
6-24 GPIO Input Qualifier – Example Diagram for QUALPRD = 1............................................................. 116
6-25 General-Purpose Input Timing ................................................................................................ 117
6-26 SPI Master Mode External Timing (Clock Phase = 0) ..................................................................... 119
6-27 SPI Master External Timing (Clock Phase = 1)............................................................................. 121
6-28 SPI Slave Mode External Timing (Clock Phase = 0)....................................................................... 123
6-29 SPI Slave Mode External Timing (Clock Phase = 1)....................................................................... 125
6-30 Relationship Between XTIMCLK and SYSCLKOUT ....................................................................... 129
6-31 Example Read Access ......................................................................................................... 132
6-32 Example Write Access ......................................................................................................... 133
6-33 Example Read With Synchronous XREADY Access ...................................................................... 135
6-34 Example Read With Asynchronous XREADY Access ..................................................................... 136
6-35 Write With Synchronous XREADY Access.................................................................................. 138
6-36 Write With Asynchronous XREADY Access ................................................................................ 139
6-37 External Interface Hold Waveform............................................................................................ 141
6-38 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK).................................................. 142
6-39 ADC Analog Input Impedance Model ........................................................................................ 146
6-40 ADC Power-Up Control Bit Timing ........................................................................................... 146
6-41 Sequential Sampling Mode (Single-Channel) Timing ...................................................................... 147
6-42 Simultaneous Sampling Mode Timing ....................................................................................... 148
6-43 McBSP Receive Timing........................................................................................................ 152
6-44 McBSP Transmit Timing ....................................................................................................... 152
6-45 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 ................................................... 153
6-46 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 ................................................... 154
6-47 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ................................................... 155
6-48 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ................................................... 156
6
List of Figures
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