TMS320F2810_12 Datasheet, PDF (153/172 Pages) Texas Instruments – Digital Signal Processors

TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
www.ti.com
SPRS174T – APRIL 2001 – REVISED MAY 2012
6.31.2 McBSP as SPI Master or Slave Timing
Table 6-52. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)⁽¹⁾
MASTER
SLAVE
NO.
UNIT
MIN MAX
MIN MAX
M30
M31
M32
M33
t_su(DRV-CKXL)
t_h(CKXL-DRV)
t_{su(BFXL-CKXH)}
t_c(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX high
Cycle time, CLKX
30
8P – 10
ns
1
8P – 10
ns
8P + 10
ns
2P
16P
ns
(1) 2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
Table 6-53. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)⁽¹⁾
NO.
PARAMETER
MASTER
MIN MAX
SLAVE
UNIT
MIN MAX
M24 t_h(CKXL-FXL)
Hold time, FSX low after CLKX low
2P
ns
M25 t_d(FXL-CKXH)
Delay time, FSX low to CLKX high
P
ns
M28 t_{dis(FXH-DXHZ)}
Disable time, DX high impedance following last data bit
from FSX high
6
6P + 6
ns
M29 t_d(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
(1) 2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
CLKX
LSB
M32
MSB
M33
M24
M25
FSX
M28
M29
DX
Bit 0
DR
Bit 0
Bit(n-1)
M30
Bit(n-1)
(n-2)
M31
(n-2)
(n-3)
(n-4)
(n-3)
(n-4)
Figure 6-45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Copyright © 2001–2012, Texas Instruments Incorporated
Electrical Specifications 153
Submit Documentation Feedback
Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812