TMS320F28069_16 Datasheet, PDF (6/177 Pages) Texas Instruments – Fast Interrupt Response and Processing

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698F – NOVEMBER 2010 – REVISED MARCH 2016
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2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from July 2, 2014 to March 22, 2016 (from E Revision (July 2014) to F Revision)
Page
• Global: Changed "CAN 2.0B" to "ISO11898-1 (CAN 2.0B)". .................................................................. 1
• Table 3-1 (Device Comparison): Changed the number of High-resolution ePWM Channels on the 80-Pin
PN/PFP packages from 6 to 8. ..................................................................................................... 7
• Table 3-1: Removed "Product status" row and associated footnote. ......................................................... 7
• Figure 4-1 (80-Pin PN and PFP Packages (Top View)): Added footnote about PowerPAD. .............................. 9
• Figure 4-2 (100-Pin PZ and PZP Packages (Top View)): Added footnote about PowerPAD. ........................... 10
• Section 4.2 (Signal Descriptions): Added "GPIO26–27" to NOTE. .......................................................... 11
• Table 4-1 (Signal Descriptions): Updated DESCRIPTION of X1, V_REFHI, V_REFLO, and V_DDIO. ............................. 11
• Section 5.1 (Absolute Maximum Ratings): Added Input voltage, V_IN (X1). ................................................. 19
• Section 5.1: Added T_stg. ........................................................................................................... 19
• Section 5.2 (ESD Ratings for TMS320F2806xU): Added section. ........................................................... 19
• Section 5.3 (ESD Ratings for TMS320F2806x, TMS320F2806xM, and TMS320F2806xF): Changed title from
"Handling Ratings" to "ESD Ratings for TMS320F2806x, TMS320F2806xM, and TMS320F2806xF". ................. 19
• Section 5.3: Updated footnotes. .................................................................................................. 19
• Section 5.4 (Recommended Operating Conditions): Removed footnote that read "V_DDIO and V_DDA should be
maintained within approximately 0.3 V of each other". ........................................................................ 20
• Section 5.6 (Power Consumption Summary): Changed section title from "Current Consumption" to "Power
Consumption Summary". .......................................................................................................... 21
• Section 5.12 (Power Sequencing): Updated paragraph that reads "There is no power sequencing requirement
needed ...". .......................................................................................................................... 29
• Table 5-10 (XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)): Added MAX value for t_f(XCO) ........ 34
• Table 5-10: Added MAX value for t_r(XCO) ......................................................................................... 34
• Table 5-15 (Flash/OTP Access Timing): Removed footnote. ................................................................. 36
• Figure 6-1 (28069 Memory Map): Added "FAST and SpinTAC Libraries" block. Changed size of Boot ROM. ........ 48
• Figure 6-2 (28068 Memory Map): Added "FAST and SpinTAC Libraries" block. Changed size of Boot ROM. ....... 49
• Figure 6-3 (28067 Memory Map): Added figure. ............................................................................... 50
• Figure 6-8 (28062 Memory Map): Added "FAST and SpinTAC Libraries" block. Changed size of Boot ROM. ........ 55
• Section 6.6.2 (Crystal Oscillator Option): Added paragraph that begins "The on-chip crystal oscillator X1 and X2
pins are 1.8-V level signals ...". ................................................................................................... 67
• Section 6.9.6.1.2 (McBSP as SPI Master or Slave Timing): Replaced "For all SPI slave modes ..." paragraphs
with "For all SPI slave modes ..." table footnotes. ............................................................................ 115
• Table 6-44 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)): Added "For all
SPI slave modes ..." footnote. ................................................................................................... 115
• Table 6-46 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)): Added "For all
SPI slave modes ..." footnote. ................................................................................................... 116
• Table 6-48 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)): Added "For all
SPI slave modes ..." footnote. ................................................................................................... 117
• Table 6-50 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)): Added "For all
SPI slave modes ..." footnote. ................................................................................................... 118
• Table 6-65 (HRCAP Registers): Added reference to footnote for HCICLR and HCIFRC. .............................. 137
• Section 7 (Applications, Implementation, and Layout): Added section. .................................................... 156
• Section 8.1.1.1 (Getting Started): Updated links. ............................................................................. 159
• Figure 8-1 (Device Nomenclature): Updated list of devices. ................................................................ 160
• Section 8.2 (Documentation Support): Added the Calculating Useful Lifetimes of Embedded Processors
Application Report (SPRABX4) to list of application reports. ............................................................... 161
• Section 8.2.1 (Receiving Notification of Document Updates): Added section. ............................................ 162
6
Revision History
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TMS320F28064 TMS320F28063 TMS320F28062