TMS320F28069_16 Datasheet, PDF (102/177 Pages) Texas Instruments – Fast Interrupt Response and Processing

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698F – NOVEMBER 2010 – REVISED MARCH 2016
www.ti.com
Table 6-36. SPI Master Mode External Timing (Clock Phase = 1)^{(1)(2)(3)(4)(5)}
SPI WHEN (SPIBRR + 1) IS EVEN
SPI WHEN (SPIBRR + 1) IS ODD
NO.
OR SPIBRR = 0 OR 2
AND SPIBRR > 3
MIN
MAX
MIN
MAX
1 t_c(SPC)M
t_w(SPCH)M
2
t_w(SPCL))M
Cycle time, SPICLK
Pulse duration, SPICLK high
(clock polarity = 0)
Pulse duration, SPICLK low
(clock polarity = 1)
4t_c(LCO)
0.5t_c(SPC)M – 10
0.5t_c(SPC)M – 10
128t_c(LCO)
0.5t_c(SPC)M
0.5t_c(SPC)M
5t_c(LCO)
0.5t_c(SPC)M – 0.5t_{c (LCO)} – 10
0.5t_c(SPC)M – 0.5t_{c (LCO)} – 10
127t_c(LCO)
0.5t_c(SPC)M – 0.5t_c(LCO)
0.5t_c(SPC)M – 0.5t_c(LCO
t_w(SPCL)M
3
t_w(SPCH)M
Pulse duration, SPICLK low
(clock polarity = 0)
Pulse duration, SPICLK high
(clock polarity = 1)
0.5t_c(SPC)M – 10
0.5t_c(SPC)M – 10
0.5t_c(SPC)M
0.5t_c(SPC)M
0.5t_c(SPC)M + 0.5t_c(LCO) – 10
0.5_tc(SPC)M + 0.5t_c(LCO) – 10
0.5t_c(SPC)M + 0.5t_c(LCO)
0.5t_c(SPC)M + 0.5t_c(LCO)
t_{su(SIMO-SPCH)M}
6
t_{su(SIMO-SPCL)M}
Setup time, SPISIMO data valid
before SPICLK high
(clock polarity = 0)
Setup time, SPISIMO data valid
before SPICLK low
(clock polarity = 1)
0.5t_c(SPC)M – 10
0.5t_c(SPC)M – 10
0.5t_c(SPC)M – 10
0.5t_c(SPC)M – 10
t_{v(SPCH-SIMO)M}
7
t_{v(SPCL-SIMO)M}
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
0.5t_c(SPC)M – 10
0.5t_c(SPC)M – 10
0.5t_c(SPC)M – 10
0.5t_c(SPC)M – 10
t_{su(SOMI-SPCH)M}
Setup time, SPISOMI before
SPICLK high (clock polarity = 0)
26
26
10
t_{su(SOMI-SPCL)M}
Setup time, SPISOMI before
SPICLK low (clock polarity = 1)
26
26
t_{v(SPCH-SOMI)M}
11
t_{v(SPCL-SOMI)M}
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
0.25t_c(SPC)M – 10
0.25_tc(SPC)M – 10
0.5t_c(SPC)M – 10
0.5_tc(SPC)M – 10
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) t_c(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 20-MHz MAX, master mode receive 10-MHz MAX
Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.
(4) t_c(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
UNIT
ns
ns
ns
ns
ns
ns
ns
102 Detailed Description
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