TLC3545_14 Datasheet, PDF (6/27 Pages) Texas Instruments – 200-KSPS Sampling Rate Built-In Conversion Clock

TLC3541, TLC3545
SLAS345 − DECEMBER 2001
timing requirements, V_DD = 5 V, V_REF = 4.096 V, SCLK frequency = 15 MHz (unless otherwise specified)
MIN TYP MAX UNIT
tcyc(SCLK) SCLK cycle time, VDD = 4.5 V to 5.5 V (see Note 3)
66
10000 ns
tw1
Pulse duration, SCLK low
27
5000 ns
tw2
Pulse duration, SCLK high
27
5000 ns
th1
Hold time, CS high after SCLK falling edge
3
ns
tsu1
Setup time, CS falling edge before the first SCLK falling edge
15
ns
th2
Hold time, CS low after 16th SCLK falling edge
5
ns
tw3
Pulse duration, CS high
0.5
SCLKs
td1
Delay time, CS falling edge to SDO MSB valid, VDD = VREF = 4.5 V, 20 pF
12
17 ns
td2
Delay time, SCLK rising edge to next SDO data bit valid, VDD = VREF = 4.5 V, 20 pF
td3
Delay time, 17th SCLK rising edge to 3-stated SDO, VDD = VREF = 4.5 V, 20 pF (see Note 4)
15 ns
20 ns
tsu3
Setup time, CS falling edge before FS rising edge (TLC3541 only)
0.5
1
SCLKs
tw4
Pulse duration, FS high (TLC3541 only)
0.5
1
SCLKs
tsu4
Setup time, FS rising edge before SCLK falling edge (TLC3541 only)
12.5
ns
th4
Hold time, FS high after SCLK falling edge (TLC3541 only)
5
ns
tsu5
Setup time, FS falling edge before 1st SCLK falling edge (TLC3541 only)
12
ns
td4
Delay time, FS rising edge to SDO MSB valid, (VDD = VREF = 4.5 V, 20 pF TLC3541 only)
15 ns
th6
Hold time, CS low after 1st SCLK falling edge
5
ns
tsu6
Setup time, CS rising edge before 9th (or the last) SCLK falling edge
5
ns
th7
Hold time, FS low after 1st SCLK falling edge (TLC3541 only)
tsu7
Setup time, FS rising edge before 9th (or the last) SCLK falling edge
5
ns
5
ns
tcyc(reset) Active CS/FS cycle time, SCLK falling edges required to initialize ADC
1
8 SCLKs
tconv
ts
NOTES:
Conversion time (20 conversion clocks based on 7.5 MHz to 12 MHz OSC)
1.67
2.67 µs
Sample time, 20 SCLKs, SCLK up to 15 MHz
1.33
200 µs
3. Timing specifications given for 40/60 to 60/40 duty cycle
4. SDO goes into the high impedance state after detection of the 17th rising SCLK edge or a rising CS edge if a 17th SCLK is not
presented.
6
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