TLC3545_14 Datasheet, PDF (12/27 Pages) Texas Instruments – 200-KSPS Sampling Rate Built-In Conversion Clock

TLC3541, TLC3545
SLAS345 − DECEMBER 2001
PRINCIPLES OF OPERATION
control and timing (continued)
sampling and conversion cycle
TLC3541:
Control via pin 1, CS (FS = 1 at the falling edge of CS) − The falling edge of CS is the start of the cycle.
Transitions on CS can occur when SCLK is high or low. The MSB may be read on the first falling SCLK edge
after CS is low. Output data changes on the rising edge of SCLK. This control method is typically used for a
microcontroller with an SPI interface, although it can also be used for a DSP. The microcontroller SPI
interface should be programmed for CPOL = 0 (serial clock inactive low) and CPHA = 1 (data valid on the
falling edge of serial clock).
Control via pin 7, FS (CS is tied/held low) − The rising edge of FS is the start of the cycle. Transitions on FS
can occur when SCLK is high or low. The MSB is presented on SDO after the rising edge of FS. The MSB
may be read on the first falling edge of SCLK after the FS falling edge. Output data changes on the rising
edge of SCLK. This is the typical configuration when the ADC is the only device on the TMS320 DSP serial
port.
Control via pin 1 and pin 7, CS and FS − Transitions on CS and FS can occur when SCLK is high or low. The
MSB is presented after the rising edge of FS. The falling edge of FS is the start of the sampling cycle. The
MSB may be read on the first falling edge of SCLK after the FS falling edge. Output data changes on the
rising edge of SCLK. This is typically used for multiple devices connected to a single TMS320 DSP serial
port.
TLC3545:
All control is provided using the CS input (pin 1) on the TLC3545. Transitions on CS can occur when SCLK is
high or low. The cycle is started on the falling edge transition on the CS input. This signal can be provided by
either a CS signal (when interfacing with an SPI microcontroller) or FS signal (when interfacing with a
TMS320 DSP). The MSB is presented to SDO on the falling edge of the signal applied to pin 1 and may be
read on the first falling SCLK edge after this input is low. Output data changes on the rising edge of SCLK.
control modes
control via pin 1 (CS, SPI interface)
All devices are compatible with this mode of operation. A falling edge on the CS input initiates the cycle. (For
the TLC3541, the FS input is tied to V_DD ). The CS input remains low for the entire sampling time plus 4 SCLK
decoding time (24 falling SCLK edges) and can then be released at any point during the remainder of the
conversion. Enough time should be allowed before the next falling CS edge so that the conversion cycle is not
terminated prematurely. The microcontroller SPI interface should be programmed for CPOL = 0 (serial clock
inactive low) and CPHA = 1 (data is valid on the falling edge of serial clock).
SCLK
CS
SDO
1
2
3
4
5
6
7
12 13
14 15 16
24
ts
tconv
SDO Data Is the Result of the Previous Sample
For TLC35xx, the LSB Is Presented on the Rising SCLK 14th Edge
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6
LSB+2 LSB+1
ÎÎÎÎ ^{LSB LSB−1 LSB−2}
t(PWRDWN)
Figure 15. SPI Cycle TIming Using the CS Input (FS = 1 for TLC3541)
1
MSB MSB−1
12
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