TLC2272 Datasheet, PDF (6/63 Pages) Texas Instruments – Advanced LinCMOS Rail-to-Rail Operational Amplifiers

TLC2272, TLC2272A, TLC2272M, TLC2272AM
TLC2274, TLC2274A, TLC2274M, TLC2274AM
SLOS190H – FEBRUARY 1997 – REVISED MARCH 2016
Recommended Operating Conditions (continued)
T_A
Operating free-air temperature
C LEVEL PARTS
I LEVEL PARTS
Q LEVEL PARTS
M LEVEL PARTS
www.ti.com
MIN
MAX
UNIT
0
70
–40
125
°C
–40
125
–55
125
6.4 Thermal Information
THERMAL METRIC⁽¹⁾
R_θJA
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
R_θJC(bot)
Junction-to-ambient thermal
resistance ⁽²⁾⁽³⁾
Junction-to-case (top) thermal
resistance ⁽²⁾⁽³⁾
Junction-to-board thermal
resistance
Junction-to-top
characterization parameter
Junction-to-board
characterization parameter
Junction-to-case (bottom)
thermal resistance
D
(SOIC)
8-PIN
115.6
61.8
55.9
14.3
55.4
—
P
(PDIP)
8-PIN
58.5
48.3
35.6
25.9
35.5
—
TLC2272
PW
(TSSOP)
8-PIN
175.8
58.8
104.3
5.9
102.6
—
FK
(LCCC)
20-PIN
U
(CFP)
10-PIN
—
—
18
121.3
—
—
—
—
—
—
—
8.68
D
(SOIC)
14-PIN
83.8
43.2
38.4
9.4
38.1
—
N
(PDIP)
14-PIN
TLC2274
PW
(TSSOP)
14-PIN
—
111.6
34
41.2
—
54.7
—
3.9
—
53.9
—
—
FK
(LCCC)
20-PIN
J
(CDIP)
14-PIN
—
—
16
16.2
—
—
—
—
—
—
—
—
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Maximum power dissipation is a function of T_J(max), θ_JA, and T_A. The maximum allowable power dissipation at any allowable ambient
temperature is P_D = (T_J(max) − T_A) / θ_JA. Operating at the absolute maximum T_J of 150°C can affect reliability.
(3) The package thermal impedance is calculated in accordance with JESD 51-7 (plastic) or MIL-STD-883 Method 1012 (ceramic).
6.5 TLC2272 and TLC2272A Electrical Characteristics V_DD = 5 V
at specified free-air temperature, V_DD = 5 V; T_A = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
V_IO
Input offset voltage
TLC2272
V_IC = 0 V, V_DD± = ±2.5 V, ^TLC2272A
V_O = 0 V, R_S = 50 Ω
TLC2272
TLC2272A
T_A = 25°C
Full Range⁽¹⁾
α_VIO
Temperature coefficient of
input offset voltage
V_IC = 0 V, V_DD± = ±2.5 V, V_O = 0 V, R_S = 50 Ω
Input offset voltage long-term drift⁽²⁾ V_IC = 0 V, V_DD± = ±2.5 V, V_O = 0 V, R_S = 50 Ω
All level parts T_A = 25°C
I_IO
Input offset current
V_IC = 0 V, V_DD± = ±2.5 V,
V_O = 0 V, R_S = 50 Ω
C level part
I level part
Q level part
T_A = 0°C to 80°C
T_A = –40°C to 85°C
T_A = –40°C to 125°C
M level part
T_A = –55°C to 125°C
All level parts T_A = 25°C
I_IB
Input bias current
V_IC = 0 V, V_DD± = ±2.5 V,
V_O = 0 V, R_S = 50 Ω
C level part
I level part
Q level part
T_A = 0°C to 80°C
T_A = –40°C to 85°C
T_A = –40°C to 125°C
M level part
T_A = –55°C to 125°C
V_ICR Common-mode input voltage
R_S = 50 Ω; |V_IO | ≤ 5 mV
T_A = 25°C
Full Range⁽¹⁾
MIN
TYP MAX UNIT
300 2500
300
950
µV
3000
1500
2
μV/°C
0.002
μV/mo
0.5
60
100
150 pA
800
800
1
60
100
150 pA
800
800
–0.3
2.5
4
V
0
2.5
3.5
(1) T_A = –55°C to 125°C.
(2) Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T_A = 150°C extrapolated to
T_A = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
6
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