THS7368_14 Datasheet, PDF (6/41 Pages) Texas Instruments – 6-Channel Video Amplifier with 3-SD and 3-SD/ED/HD/Full-HD Filters and 6-dB Gain

THS7368
SBOS497 – DECEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS: V_S+ = +3.3 V (continued)
At T_A = +25°C, R_L = 150 Ω to GND, Filter mode, and dc-coupled input/output, unless otherwise noted.
THS7368
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
DC PERFORMANCE
Biased output voltage
Input voltage range
V_IN = 0 V, SD channels
V_IN = 0 V, SF channels
DC input, limited by output
200
305
400
200
300
400
–0.1/1.46
Sync-tip clamp charge current
Input impedance
V_IN = –0.1 V, SD channels
V_IN = –0.1 V, SF channels
140
200
280
400
800 || 2
OUTPUT CHARACTERISTICS
High output voltage swing
Low output voltage swing
Output current (sourcing)
Output current (sinking)
POWER SUPPLY
R_L = 150 Ω to +1.65 V
R_L = 150 Ω to GND
R_L = 75 Ω to +1.65 V
R_L = 75 Ω to GND
R_L = 150 Ω to +1.65 V (V_IN = –0.2 V)
R_L = 150 Ω to GND (V_IN = –0.2 V)
R_L = 75 Ω to +1.65 V (V_IN = –0.2 V)
R_L = 75 Ω to GND (V_IN = –0.2 V)
R_L = 10 Ω to +1.65 V
R_L = 10 Ω to +1.65 V
3.15
2.85
3.1
3.1
3
0.06
0.05
0.12
0.1
0.05
80
70
Operating voltage
2.6
3.3
5.5
V_IN = 0 V, all channels on
18.8
Total quiescent current, no load
V_IN = 0 V, SD channels on, SF channels off
5.6
V_IN = 0 V, SD channels off, SF channels on
13.2
V_IN = 0 V, all channels off, V_DISABLE = 3 V
Power-supply rejection ratio
(PSRR)
At dc
LOGIC CHARACTERISTICS⁽⁶⁾
23.4
6.9
16.5
0.1
52
28.5
9
19.5
10
V_IH
V_IL
I_IH
I_IL
Disable time
Disabled or Bypass engaged
Enabled or Bypass disengaged
Applied voltage = 3.3 V
Applied voltage = 0 V
1.6
1.4
0.75
0.6
1
1
150
Enable time
150
Bypass/filter switch time
15
(6) The logic input pins default to a logic '0' condition when left floating.
TEST
UNITS LEVEL⁽¹⁾
mV
A
mV
A
V
C
μA
A
μA
A
kΩ || pF
C
V
C
V
A
V
C
V
C
V
C
V
A
V
C
V
C
mA
C
mA
C
V
B
mA
A
mA
A
mA
A
μA
A
dB
C
V
A
V
A
μA
C
μA
C
ns
C
ns
C
ns
C
FILTER 1
0
0
1
1
X
FILTER 2
0
1
0
1
X
Table 1. TRUTH TABLE: V_S+ = +3.3 V⁽¹⁾
BYPASS SF⁽²⁾
DESCRIPTION
0
Selects the standard definition filter (9.5 MHz) for the SF channels
0
Selects the enhanced definition filter (18 MHz) for the SF channels
0
Selects the high definition filter (36 MHz) for the SF channels
0
Selects the full/true high-definition filter (72 MHz) for the SF channels
1
Bypasses the filters for the SF channels
(1) The logic input pins default to a logic '0' condition when left floating.
(2) SF indicates selectable filter.
6
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