THS6226A Datasheet, PDF (6/32 Pages) Texas Instruments – THS6226A Gated-Class H, Dual-Port VDSL2 Line Driver

THS6226A
SBOS643A – APRIL 2014 – REVISED MAY 2014
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Power-supply voltage range
Operating junction temperature
Class H
Class AB
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MIN
NOM
MAX UNIT
10
12.6
V
10
15
V
–40
130
°C
6.4 Thermal Information
THERMAL METRIC⁽¹⁾
THS6226A
RHB (VQFN)
UNIT
32 PINS
R_θJA
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
R_θJC(bot)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
35.1
22.1
7.0
°C/W
0.3
6.9
1.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics: V_S = +12 V
At T_A = 25°C, R_MATCH = 10.2 Ω, transformer turn ratio 1:1.4, R_L = 100-Ω differential at transformer output, full bias mode, and
active impedance circuit configuration, unless otherwise noted. Each port is tested independently.
PARAMETER
CONDITIONS
TEST
MIN
TYP
MAX UNIT
LEVEL ⁽¹⁾
AC PERFORMANCE
Small-signal bandwidth, –3 dB
V_O = 2 V_PP, differential at
OUTCD and OUTAB, gain = 19 V/V
97
MHz
C
SR
HD2
HD3
0.1-dB bandwidth flatness
Large-signal bandwidth
Slew rate (10% to 90% level)
Rise-and-fall time
Second-harmonic distortion
Third-harmonic distortion
Differential input voltage noise
V_O = 2 V_PP
V_O = 7.5 V_PP
V_O = 15-V step, differential
V_O = 2 V_PP
Full bias, f = 1 MHz, V_O = 2 V_PP,
R_L = 60-Ω differential
Full bias, f = 5 MHz, V_O = 2 V_PP,
R_L = 60-Ω differential
Full bias, f = 1 MHz, V_O = 2 V_PP,
R_L = 60-Ω differential
Full bias, f = 5 MHz, V_O = 2 V_PP,
R_L = 60-Ω differential
f = 1 MHz, input-referred
30
80
1750
3.6
–87
–73
–83
–71
6.5
MHz
C
MHz
C
V/μs
C
ns
C
dBc
C
dBc
C
dBc
C
dBc
C
nV/√Hz
C
DC PERFORMANCE
Differential gain
Differential gain error⁽²⁾
V_IO
Input offset voltage
Input offset voltage drift
Closed-loop configuration
T_A = 25°C
T_A = 25°C
T_A = –40°C to 85°C
19
V/V
C
±8%
A
±1
±10
mV
A
±11
mV
B
15 μV/°C
B
Input offset voltage matching
INPUT CHARACTERISTICS
Channels 1 to 2 and 3 to 4 only,
T_A = 25°C
±1
±10
mV
A
Noninverting input resistance
2 || 2
kΩ || pF
C
Input bias voltage
T_A = 25°C
5.8
6
6.2
V
A
(1) Test levels: (A) 100% tested at 25°C. Overtemperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
(2) Negative feedback loop only.
6
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