LMK00306 Datasheet, PDF (6/25 Pages) Texas Instruments – 3-GHz 6-Output Differential Clock Buffer/Level Translator

Symbol
Parameter
Conditions
Min Typ Max Units
I_{CCO_LVDS}
Additive Output Supply Current,
Per LVDS Bank Enabled
20
27.5
mA
I_{CCO_HCSL}
I_{CCO_CMOS}
Additive Output Supply Current,
Per HCSL Bank Enabled
Additive Output Supply Current,
LVCMOS Output Enabled
Includes Output Bank Bias and Load
Currents, R_T = 50 Ω on all outputs in bank
Vcco =
200 MHz,
3.3 V ± 5%
C_L = 5 pF
Vcco =
2.5 V ± 5%
50
65
mA
9
10
mA
7
8
mA
Power Supply Ripple Rejection (PSRR)
PSRR_PECL
Ripple-Induced
Phase Spur Level (Note 13)
Differential LVPECL Output
156.25 MHz
312.5 MHz
-65
dBc
-63
PSRR_LVDS
Ripple-Induced
Phase Spur Level (Note 13)
Differential LVDS Output
100 kHz, 100 mVpp
Ripple Injected on
Vcco, Vcco = 2.5 V
156.25 MHz
312.5 MHz
-76
dBc
-74
PSRR_HCSL
Ripple-Induced
Phase Spur Level (Note 13)
Differential HCSL Output
156.25 MHz
312.5 MHz
-72
dBc
-63
CMOS Control Inputs (CLKin_SELn, CLKoutX_TYPEn, REFout_EN)
V_IH
High-Level Input Voltage
1.6
Vcc
V
V_IL
Low-Level Input Voltage
GND
0.4
V
I_IH
High-Level Input Current
V_IH = Vcc, Internal pull-down resistor
50
µA
I_IL
Low-Level Input Current
V_IL = 0 V, Internal pull-down resistor
-5
0.1
µA
Clock Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)
f_CLKin
Input Frequency Range
(Note 20)
Functional up to 3.1 GHz
Output frequency range and timing specified
per output type (refer to LVPECL, LVDS,
DC
HCSL, LVCMOS output specifications)
3.1
GHz
V_IHD
Differential Input High Voltage
V_ILD
Differential Input Low Voltage
V_ID
Differential Input Voltage Swing
(Note 14)
CLKin driven differentially
GND
0.15
Vcc
V
V
1.3
V
V_CMD
Differential Input
Common Mode Voltage
V_ID = 150 mV
V_ID = 350 mV
0.5
Vcc -
1.2
0.5
Vcc -
V
1.1
V_IH
Single-Ended Input
High Voltage
V_ID = 800 mV
0.5
V_CM +
0.15
Vcc -0.9
Vcc
V
V_IL
Single-Ended Input
Low Voltage
CLKinX driven single-ended,
CLKinX* AC coupled to GND
GND
V_CM
V
-0.15
V_CM
Single-Ended Input
Common Mode Voltage
0.5
Vcc -
1.2
V
f_CLKin0 = 100 MHz
-84
ISO_MUX
Mux Isolation,
CLKin0 to CLKin1
f_OFFSET > 50 kHz,
P_CLKinX = 0 dBm
f_CLKin0 = 200 MHz
f_CLKin0 = 500 MHz
-82
-71
dBc
f_CLKin0 = 1000 MHz
-65
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