LM3537_13 Datasheet, PDF (6/33 Pages) Texas Instruments – 8-Channel WLED Driver with Four Integrated LDOs

LM3537
SNVS634B – JUNE 2011 – REVISED MAY 2013
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LOGIC INTERFACE CHARACTERISTICS⁽¹⁾⁽²⁾
Symbol
Parameter
I²C-Compatible Interface Timing Specifications (SCL, SDA)⁽³⁾
t₁
SCL (Clock Period)
See ⁽⁴⁾
t₂
Data In Setup Time to SCL High
t₃
Data Out stable After SCL Low
t₄
SDA Low Setup Time to SCL Low
(Start)
Condition
t₅
SDA High Hold Time After SCL High
(Stop)
I²C-Compatible Interface Voltage Specifications (SCL, SDA)
V_IL
Input Logic Low "0"
V_IH
Input Logic High "1"
V_OL
Output Logic Low "0"
Logic inputs HWEN and PWM
2.7V ≤ V_{IN_A} ≤ 5.5V
2.7V ≤ V_{IN_A} ≤ 5.5V
I_LOAD = 3mA
V_HWEN HWEN Voltage Thresholds
2.7V ≤ V_{IN_A} ≤ 5.5V
Reset
Normal Operation
V_PWM PWM Voltage Thresholds
2.7V ≤ V_{IN_A} ≤ 5.5V
LEDs Off
LEDs On
ALS interrupt
V_OL-INT Interrupt Output Logic Low '0'
Logic outputs GPO1, GPO2⁽⁵⁾
I_LOAD = 3mA
V_OL
Output Low Level
I_OUT = 3 mA
V_OH
Output High Level
I_OUT = −2 mA
Min
Typ
Max Units
2.5
µs
100
ns
0
ns
100
ns
100
ns
0
1.25
0.45
V
V_{IN_A}
V
400
mV
0
0.45
V
1.2
V_{IN_A}
0
0.45
V
1.2
V_{IN_A}
400
mV
0.3
0.5
V
V_{OUT_S} V_{OUT_S}
−0.5
–0.3
V
(1) All voltages are with respect to the potential at the GND pins.
(2) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most
likely norm.
(3) SCL and SDA should be glitch-free in order for proper device control to be realized. See Figure 2 for timing specification details.
(4) SCL is tested with a 50% duty-cycle clock.
(5) V_{OUT_S} = SBIAS pin output voltage. The voltage level of the GPOs depends on the sbias_en-bit: '1'; GPOs will behave as push-pull
outputs and will reference the high-side to the voltage of SBIAS. '0'; GPOs will act as open-drain outputs (default). In the open-drain
configuration, they can be high-side referenced to any voltage equal to, or less than, the VIN_A of the LM3537. Output High Level (V_OH)
specification is valid only for push-pull -type outputs.
6
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