LM3537_13 Datasheet, PDF (19/33 Pages) Texas Instruments – 8-Channel WLED Driver with Four Integrated LDOs

LM3537
www.ti.com
SNVS634B – JUNE 2011 – REVISED MAY 2013
The power input voltage applied between V_{IN_C} and GND should be at least 0.3V above the output voltage of the
regulators. The bias input voltage applied between V_{IN_B} and GND should be equal to V_{IN_A}, and at least 0.3V
above the output voltage of the regulators.
V_{IN_C}
PASS
ELEMENT
REGULATED
OUTPUT
V_{IN_B}
NOISE
SUPPRESSION
VOLTAGE
CONTROL
VREF
V_{IN_B} supplies internal circuitry. V_{IN_C}, the power input voltage, is regulated to the fixed output voltage.
Figure 6. LDO Block Diagram
I²C-Compatible Interface
STOP AND START CONDITIONS
The LM3537 is controlled via an I²C-compatible interface. START and STOP ) conditions classify the beginning
and the end of the I²C session. A START condition is defined as SDA transitioning from HIGH to LOW while SCL
is HIGH. A STOP condition is defined as SDA transitioning from LOW to HIGH while SCL is HIGH. The I²C
master always generates START and STOP conditions. The I²C bus is considered busy after a START condition
and free after a STOP condition. During data transmission, the I²C master can generate repeated START
conditions. A START and a repeated START conditions are equivalent function-wise. The data on SDA must be
stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed
when SCL is LOW.
Figure 7. Start and Stop Sequences
I²C-COMPATIBLE CHIP ADDRESS
The chip address for the LM3537 is 0111000 (38h). After the START condition, the I²C master sends the 7-bit
chip address followed by a read or write bit (R/W). R/W= 0 indicates a WRITE and R/W = 1 indicates a READ.
The second byte following the chip address selects the register address to which the data will be written. The
third byte contains the data for the selected register.
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