DS92LV040A_14 Datasheet, PDF (6/17 Pages) Texas Instruments – 4 Channel Bus LVDS Transceiver

DS92LV040A
SNOS521D – JANUARY 2001 – REVISED APRIL 2013
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signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. (Note
the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely
solely on the autoroute function for differential traces. Carefully review dimensions to match differential
impedance and provide isolation for the differential lines. Minimize the number of vias and other discontinuity
on the line. Avoid 90° turns (these cause impedance discontinuity). Use arcs or 45° bevels. Within a pair of
traces, the distance between the two traces should be minimized to maintain common-mode rejection of the
receivers. On the printed circuit board, this distance should remain constant to avoid discontinuity in
differential impedance. Minor violations at connection points are allowable.
• Stub Length: Stub lengths should be kept to a minimum. The typical transition time of the DS92LV040A
BLVDS output is 0.75ns (20% to 80%). The extrapolated 100 percent time is 0.75/0.6 or 1.25ns. For a
general approximation, if the electrical length of a trace is greater than 1/5 of the transition edge, then the
trace is considered a transmission line. For example, 1.25ns/5 is 250 picoseconds. Let velocity equal 160ps
per inch for a typical loaded backplane. Then maximum stub length is 250ps/160ps/in or 1.56 inches. To
determine the maximum stub for your backplane, you need to know the propagation velocity for the actual
conditions (refer to application notes AN 905 and AN 808).
PACKAGE and SOLDERING INFORMATION:
• Refer to packaging application note AN-1187 (SNOA401). This application note details the package
attachment methods to achieve the correct solderability and thermal results.
Table 1. Functional Table
MODE SELECTED
DRIVER MODE
RECEIVER MODE
TRI-STATE MODE
LOOP BACK MODE
DE
RE
H
H
L
L
L
H
H
L
Table 2. Transmitter Mode
INPUTS
DE
D_IN
H
L
H
H
H
0.8V< D_IN <2.0V
L
X
DO+
L
H
X
Z
OUTPUTS
DO−
H
L
X
Z
Table 3. Receiver Mode
INPUTS
RE
(RI+) – (RI−)
L
L (< −70 mV)
L
H (> 0 mV)
L
−70 mV < V_ID < 0 mV
H
X
OUTPUT
L
H
X
Z
Test Circuits and Timing Waveforms
Figure 1. Differential Driver DC Test Circuit
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