DS92LV040A_14 Datasheet, PDF (4/17 Pages) Texas Instruments – 4 Channel Bus LVDS Transceiver

DS92LV040A
SNOS521D – JANUARY 2001 – REVISED APRIL 2013
AC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified.⁽¹⁾
Symbol
Parameter
Conditions ⁽²⁾
Min
DIFFERENTIAL DRIVER TIMING REQUIREMENTS
t_PHLD
t_PLHD
t_SKD1
Differential Prop. Delay High to Low⁽³⁾
Differential Prop. Delay Low to High⁽³⁾
Differential Skew |t_PHLD–t_PLHD| (duty cycle)⁽⁴⁾
(3)
t_CCSK
t_TLH
t_THL
t_PHZ
t_PLZ
t_PZH
t_PZL
f_MAXD
Channel to Channel Skew (all 4 channels)⁽³⁾⁽⁵⁾
Transition Time Low to High (20% to 80%)
Transition Time High to Low (80% to 20%)
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
Ensured operation per data sheet up to the Min. Duty Cycle
45/55%,Transition time ≤ 25% of period⁽³⁾
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
t_PHLDR
t_PLHDR
t_SDK1R
t_CCSKR
t_TLHR
t_THLR
Differential Prop. Delay High to Low⁽³⁾
Differential Prop Delay Low to High⁽³⁾
Differential Skew |t_PHLD–t_PLHD| (duty cycle)⁽⁴⁾⁽³⁾
Channel to Channel Skew (all 4 channels)⁽³⁾⁽⁵⁾
Transition Time Low to High (10% to 90%)⁽³⁾
Transition Time High to Low (90% to 10%)⁽³⁾
t_PHZ
Disable Time High to Z
t_PLZ
Disable Time Low to Z
t_PZH
Enable Time Z to High
t_PZL
Enable Time Z to Low
f_MAXR
Ensured operation per data sheet up to the Min. Duty Cycle
45/55%,Transition time ≤ 25% of period⁽³⁾
R_L = 27Ω,
Figure 2, Figure 3,
C_L = 10 pF
R_L = 27Ω,
Figure 4, Figure 5,
C_L = 10 pF
Figure 6, Figure 7,
C_L = 15 pF
R_L = 500Ω,
Figure 8, Figure 9,
C_L = 15 pF
1.0
1.0
0.4
0.4
85
1.6
1.6
0.850
0.850
85
Typ
1.5
1.5
80
220
0.75
0.75
5.0
5.0
5.0
5.0
125
2.4
2.4
85
140
1.250
1.030
3.0
3.0
3.0
3.0
125
www.ti.com
Max
Unit
s
2.3
ns
2.3
ns
160 ps
400 ps
1.3
ns
1.3
ns
10
ns
10
ns
10
ns
10
ns
MHz
3.2
ns
3.2
ns
160 ps
300 ps
2.0
ns
2.0
ns
10
ns
10
ns
10
ns
10
ns
MHz
(1) Generator waveforms for all tests unless otherwise specified: f = 25 MHz, Z_O = 50Ω, t_r, t_f = <1.0 ns (0%–100%). To ensure fastest
propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster
than 3ns/V. In general, the faster the input edge rate, the better the AC performance.
(2) C_L includes probe and fixture capacitance.
(3) Propagation delays, transition times, and receiver threshold are ensured by design and characterization.
(4) t_SKD1 |t_PHLD–t_PLHD| is the worst case pulse skew (measure of duty cycle) over recommended operation conditions.
(5) Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.
4
Submit Documentation Feedback
Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV040A