DS92LV040A_14 Datasheet, PDF (5/17 Pages) Texas Instruments – 4 Channel Bus LVDS Transceiver

DS92LV040A
www.ti.com
SNOS521D – JANUARY 2001 – REVISED APRIL 2013
APPLICATIONS INFORMATION
General application guidelines and hints may be found in the following application notes: AN-808 (SNLA028),
AN-977 (SNLA166), AN-971 (SNLA165), and AN-903 (SNLA034).
BLVDS drivers and receivers are intended to be used in a differential backplane configuration. Transceivers or
receivers are connected to the driver through a balanced media such as differential PCB traces. Typically, the
characteristic differential impedance of the media (Zo) is in the range of 50Ω to 100Ω. Two termination resistors
of ZoΩ each are placed at the ends of the transmission line backplane. The termination resistor converts the
current sourced by the driver into a voltage that is detected by the receiver. The effects of mid-stream
connector(s), cable stub(s), and other impedance discontinuity as well as ground shifting, noise margin limits,
and total termination loading must be taken into account.
The DS92LV040A differential line driver is a balanced current mode design. A current mode driver, generally
speaking has a high output impedance (100 ohms) and supplies a reasonably constant current for a range of
loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). The current is
switched through the load in one direction to produce a logic state and in the other direction to produce the other
logic state. The output current is typically 12 mA. The current changes as a function of load resistor. The current
mode requires (as discussed above) that a resistive termination be employed to terminate the signal and to
complete the loop. Unterminated configurations are not allowed. The 12 mA loop current will develop a
differential voltage of about 300mV across a 27Ω (double terminated 54Ω differential transmission backplane)
effective resistance, which the receiver detects with a 230 mV minimum differential noise margin neglecting
resistive line losses (driven signal minus receiver threshold (300 mV – 70 mV = 230 mV)). The signal is centered
around +1.2V (Driver Offset, VOS ) with respect to ground. Note that the steady-state voltage (VSS ) peak-to-
peak swing is twice the differential voltage (VOD ) and is typically 600 mV.
The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its
quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver
increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows
between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed
current between its output without any substantial overlap current. This is similar to some ECL and PECL
devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires 80% less
current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing
RS-422 drivers. The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower
power state when the transmission of data is not required.
There are a few common practices which should be implied when designing PCB for Bus LVDS signaling.
Recommended practices are:
• Use at least 4 PCB board layer (Bus LVDS signals, ground, power and TTL signals).
• Keep drivers and receivers as close to the (Bus LVDS port side) connector as possible.
• Bypass each Bus LVDS device and also use distributed bulk capacitance between power planes. Surface
mount capacitors placed close to power and ground pins work best. Three or more high frequency, multi-layer
ceramic (MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in parallel should be used between each V_CC and
ground.
– Multiple vias should be used to connect V_CC and Ground planes to the pads of the by-pass capacitors.
– In addition, it may be necessary to randomly distribute by-pass capacitors of different values (200pF to
1000pF) to achieve different resonant frequencies.
• Use the termination resistor which best matches the differential impedance of your transmission line.
• Leave unused Bus LVDS receiver inputs open (floating). Limit traces on unused inputs to <0.5 inches.
• Isolate TTL signals from Bus LVDS signals
MEDIA (CONNECTOR or BACKPLANE) SELECTION:
• The backplane and connectors should have a matched differential impedance. Use controlled impedance
traces which match the differential impedance of your transmission medium (ie. backplane or cable) and
termination resistor(s). Run the differential pair trace lines as close together as possible as soon as they leave
the IC . This will help eliminate reflections and ensure noise is coupled as common-mode. In fact, we have
seen that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since
magnetic field cancellation is much better with the closer traces. Plus, noise induced on the differential lines is
much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths
between traces to reduce skew. Skew between the signals of a pair means a phase difference between
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