DS90CP02_15 Datasheet, PDF (6/16 Pages) Texas Instruments – 1.5 Gbps 2x2 LVDS Crosspoint Switch

DS90CP02
SNLS267A – NOVEMBER 2008 – REVISED MARCH 2013
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
LVTTL DC SPECIFICATIONS (SEL0, SEL1, EN1, EN2)
V_IH
High Level Input Voltage
V_IL
Low Level Input Voltage
I_IH
High Level Input Current
V_IN = V_DD = V_DDMAX
I_IL
Low Level Input Current
V_IN = V_SS, V_DD = V_DDMAX
C_IN1
Input Capacitance
Any Digital Input Pin to V_SS
V_CL
Input Clamp Voltage
I_CL = −18 mA
LVDS INPUT DC SPECIFICATIONS (IN0±, IN1±)
V_TH
Differential Input High Threshold ⁽²⁾ V_CM = 0.8V or 1.2V or 3.55V, V_DD = 3.6V
V_TL
Differential Input Low Threshold
V_CM = 0.8V or 1.2V or 3.55V, V_DD = 3.6V
V_ID
Differential Input Voltage
V_CM = 0.8V to 3.55V, V_DD = 3.6V
V_CMR
Common Mode Voltage Range
V_ID = 150 mV, V_DD = 3.6V
C_IN2
Input Capacitance
IN+ or IN− to V_SS
I_IN
Input Current
V_IN = 3.6V, V_DD = V_DDMAX or 0V
V_IN = 0V, V_DD = V_DDMAX or 0V
LVDS OUTPUT DC SPECIFICATIONS (OUT0±, OUT1±)
V_OD
Differential Output Voltage,
0% Pre-emphasis ⁽²⁾
R_L = 100Ω between OUT+ and OUT−
ΔV_OD
V_OS
ΔV_OS
Change in V_OD between
Complementary States
Offset Voltage ⁽³⁾
Change in V_OS between
Complementary States
I_OS
Output Short Circuit Current, One OUT+ or OUT− Short to GND
Complementary Output
C_OUT
Output Capacitance
OUT+ or OUT− to GND when TRI-
STATE
SUPPLY CURRENT (Static)
I_CC0
Supply Current
All inputs and outputs enabled and
active, terminated with differential load of
100Ω between OUT+ and OUT-.
I_CC1
Supply Current - one channel
powered down
Single channel crossover switch or single
channel repeater modes (1 channel
active, one channel in power down mode)
I_CC2
Supply Current - one input powered Splitter mode (One input powered down,
down
both outputs active)
I_CCZ
TRI-STATE Supply Current
Both input/output Channels in Power
Down Mode
SWITCHING CHARACTERISTICS—LVDS OUTPUTS (Figure 4, Figure 5)
t_LHT
Differential Low to High Transition Use an alternating 1 and 0 pattern at 200
Time
Mb/s, measure between 20% and 80% of
t_HLT
Differential High to Low Transition
V_OD.
Time
t_PLHD
t_PHLD
Differential Low to High Propagation
Delay
Differential High to Low Propagation
Delay
Use an alternating 1 and 0 pattern at 200
Mb/s, measure at 50% V_OD between
input to output.
t_SKD1
Pulse Skew
|t_PLHD–t_PHLD|
2.0
GND
−10
−10
−1.5
−100
100
0.05
−10
−10
250
−35
1.09
−35
70
50
0.5
0.5
Typ
(1)
3.5
−0.8
0
0
3.5
400
1.25
−60
5.5
42
22
30
1.4
150
135
2.4
2.4
55
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Max
Units
V_DD
V
0.8
V
+10
µA
+10
µA
pF
V
100
mV
mV
mV
3.55
V
pF
+10
µA
+10
µA
575
mV
35
mV
1.475
V
35
mV
-90
mA
pF
60
mA
30
mA
40
mA
2.5
mA
215
ps
180
ps
3.5
ns
3.5
ns
120
ps
(1) Typical parameters are measured at V_DD = 3.3V, T_A = 25°C. They are for reference purposes, and are not production-tested.
(2) Differential output voltage V_OD is defined as ABS(OUT+–OUT−). Differential input voltage V_ID is defined as ABS(IN+–IN−).
(3) Output offset voltage V_OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
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