DS80EP100_14 Datasheet, PDF (6/21 Pages) Texas Instruments – 5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables

DS80EP100
SNLS279B – JULY 2007 – REVISED MAY 2008
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SYMMETRIC I/O STRUCTURES
The symmetry of the passive equalization network allows bi-directional operation. Signals receive equal
compensation regardless of the direction of data flow. (See Simplified Block Diagram).
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS AND NO CONNECT PADS
The differential I/Os must have a controlled differential impedance of 100Ω. It is preferable to route all differential
lines exclusively on one layer of the board. The use of vias should be avoided if possible. If vias must be used,
they should be used sparingly and must be placed symmetrically for each side of a given differential pair.
Differential signals should be routed away from other signals and noise sources on the printed circuit board. Pin
2, Pin 5, and the center DAP have to be left as no connect. Therefore, do not connect the landing pads of these
pins to the power or ground plane. See AN-1187 for additional information on the LLP package.
0.5
Unequalized
0.4
0.3
10 Gbps
8 Gbps
0.2
Equalized
0.1
0
0
5
10 15 20 25 30
FR4 LENGTH (in)
Figure 6. Residual Deterministic Jitter
vs.
FR4 Length
0.5
0.4
0.3
Unequalized
0.2
6.25 Gbps
5 Gbps
0.1
0
0
Equalized
5 10 15 20 25 30
FR4 LENGTH (in)
6
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Figure 7. Residual Deterministic Jitter
vs.
FR4 Length
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