DS80EP100_14 Datasheet, PDF (5/21 Pages) Texas Instruments – 5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables

DS80EP100
www.ti.com
SNLS279B – JULY 2007 – REVISED MAY 2008
Table 1. Table 1. Typical Through Response
Frequency (GHz)
0.1
0.5
1
1.5
2
3
4
5
6
7
8
9
10
DS80EP100 Attenuation Typ (dB)
-8.25
-7.64
-6.12
-4.68
-3.57
-2.22
-1.66
-1.53
-1.77
-2.28
-2.8
-3.47
-3.91
Block Diagram
Z3
IOA+
Z1
Z1
IOB+
A
Z2
B
IOA-
Z1
Z1
IOB-
Z3
Figure 5. Simplified Block Diagram
Application Information
DS80EP100 DEVICE DESCRIPTION
The DS80EP100 Power-Saver equalizer is a passive network circuit composed of resistive, capacitive, and
inductive components (See Figure 5). A Differential bridged T-network compensates for the transmission medium
losses and minimizes medium-induced deterministic jitter with FR4 and cables. The equalizer attenuates low
frequency signals and is a bandpass filter at the resonant frequency. The response is linear and symmetric.
I/O TERMINATIONS
The DS80EP100 I/O impedance is 100Ω differential. The equalizer is designed for 100Ω-balanced differential
signals and is not intended for single-ended transmission.
LINEAR COMPENSATION
The unique linear compensation feature of the DS80EP100 combined with the tiny package allows maximum
flexibility in placement. The equalizer can be placed anywhere in the data path and will provide the same
compensation at the receiving circuit. (See Simplified Application Diagram)
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Links: DS80EP100
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