DRV8821_16 Datasheet, PDF (6/32 Pages) Texas Instruments – Dual Stepper Motor Controller and Driver

DRV8821
SLVS912J – JANUARY 2009 – REVISED JANUARY 2016
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I_OCP
Overcurrent protect level
t_OCP
Overcurrent protect trip time
t_MD
Mixed decay percentage
Measured from beginning of PWM cycle
VREF INPUT/CURRENT CONTROL ACCURACY
I_REF
xVREF input current
ΔI_CHOP Chopping current accuracy
xVREF = 3.3 V
xVREF = 2.5 V, derived from V3P3;
71% to 100% current
xVREF = 2.5 V, derived from V3P3;
20% to 56% current
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MIN
1.5
2.5
–3
–5%
–10%
TYP
3
75%
MAX
4.5
UNIT
A
μs
3 μA
5%
10%
6.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted)
1
f_STEP
2
t_WH(STEP)
3
t_WL(STEP)
4
t_SU(STEP)
5
t_H(STEP)
6
t_WAKE
Step frequency
Pulse duration, xSTEP high
Pulse duration, xSTEP low
Setup time, command to xSTEP rising
Hold time, command to xSTEP rising
Wakeup time, SLEEPn inactive to xSTEP
MIN
MAX UNIT
200 kHz
2.5
μs
2.5
μs
200
ns
200
ns
1
ms
6.7 Dissipation Ratings
BOARD
Low-K ⁽¹⁾
Low-K ⁽²⁾
High-K ⁽³⁾
High-K ⁽⁴⁾
PACKAGE
DCA
R_θJA
75.7°C/W
32°C/W
30.3°C/W
22.3°C/W
DERATING FACTOR
ABOVE T_A = 25°C
13.2 mW/°C
31.3 mW/°C
33 mW/°C
44.8 mW/°C
T_A < 25°C
1.65 W
3.91 W
4.13 W
5.61 W
T_A = 70°C
1.06 W
2.50 W
2.48 W
3.59 W
T_A = 85°C
0.86 W
2.03 W
2.15 W
2.91 W
(1) The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with no backside copper.
(2) The JEDEC Low-K board used to derive this data was a 76-mm x 114-mm, 2-layer, 1.6-mm thick PCB with 25-cm² 2-oz copper on back
side.
(3) The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with no backside copper and
solid 1-oz internal ground plane.
(4) The JEDEC High-K board used to derive this data was a 76-mm x 114-mm, 4-layer, 1.6-mm thick PCB with 25-cm² 1-oz copper on back
side and solid 1-oz internal ground plane.
1
2
3
xSTEP
xDIR, xUSMx
45
ABENBLn
& CDENBLn
6
6
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Figure 1. Timing Diagram
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