DRV8804PWP Datasheet, PDF (6/18 Pages) Texas Instruments – QUAD SERIAL INTERFACE LOW-SIDE DRIVER IC

DRV8804
SLVSAW4C – JULY 2011 – REVISED FEBRUARY 2012
TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
NO.
PARAMETER
DESCRIPTION
1 t_CYC
2 t_CLKH
3 t_CLKL
4
t_SU(SDATIN)
5
t_H(SDATIN)
6
t_D(SDATOUT)
7
t_W(LATCH)
8
t_OE(ENABLE)
9
t_D(LATCH)
-
t_RESET
10 t_D(RESET)
11 t_STARTUP
Clock cycle time
Clock high time
Clock low time
Setup time, SDATIN to SCLK
Hold time, SDATIN to SCLK
Delay time, SCLK to SDATOUT
Pulse width, LATCH
Enable time, nENBL to output low
Delay time, LATCH to output change
RESET pulse width
Reset delay before clock
Startup delay VM applied before clock
(1) Not production tested.
RESET
VM
SCLK
SDATIN
SDATOUT
10
11
1
2
3
Data in
valid
45
Data out valid
nENBL
LATCH
OUTx
8
6
Figure 1. DRV8804 Timing Requirements
www.ti.com
MIN MAX UNIT
62
ns
25
ns
25
ns
5
ns
1
ns
15 ns
200
ns
50 ns
50 ns
20
µs
20
µs
55
µs
7
9
6
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