DAC8812 Datasheet, PDF (6/29 Pages) Texas Instruments – Dual, Serial Input 16-Bit Multiplying Digital-to-Analog Converter

DAC8812
SBAS349D – AUGUST 2005 – REVISED JANUARY 2016
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Electrical Characteristics (continued)
V_DD = 2.7 V to 5.5 V, I_OUTX = Virtual GND, A_GNDX = 0 V, V_REFA, B = 10 V, T_A = full operating temperature range, unless
otherwise noted.
PARAMETER
CONDITIONS
MIN TYP MAX UNIT
SUPPLY CHARACTERISTICS
V_{DD RANGE}
Power supply range
I_DD
Positive supply current
P_DISS
Power dissipation
P_SS
Power supply sensitivity
AC CHARACTERISTICS^{(2) (3)}
Logic inputs = 0 V, V_DD = 4.5 V to 5.5 V
Logic inputs = 0 V, V_DD = 2.7 V to 3.6 V
Logic inputs = 0 V
ΔV_DD = ±5%
2.7
5.5
V
2
5
μA
1
2.5
μA
0.0275
mW
0.006%
To ±0.1% of full-scale,
Data = 0000h to FFFFh to 0000h
t_s
Output voltage settling time
To ±0.0015% of full-scale,
Data = 0000h to FFFFh to 0000h
0.3
µs
0.5
Q_G
BW –3 dB
DAC glitch impulse
Reference multiplying BW
Feedthrough error
V_REFx = 10 V, data = 7FFFh to 8000h to 7FFFh
V_REFx = 100 mV_RMS, data = FFFFh, C_FB = 3 pF
Data = 0000h, V_REFx = 100 mV_RMS,
f = 100 kHz
5
nV-s
10
MHz
–70
dB
Crosstalk error
Data = 0000h, V_REFB = 100 mV_RMS,
Adjacent channel, f = 100 kHz
–100
dB
Q_D
THD
e_n
Digital feedthrough
Total harmonic distortion
Output spot noise voltage
CS = 1 and f_CLK = 1 MHz
V_REF = 5 V_PP, data = FFFFh, f = 1 kHz
f = 1 kHz, BW = 1 Hz
1
–105
12
nV-s
dB
nV/√Hz
(3) All ac characteristic tests are performed in a closed-loop system using a THS4011 I-to-V converter amplifier.
7.6 Timing Requirements
See Figure 1
INTERFACE TIMING⁽¹⁾
t_CH
t_CL
t_CSS
t_CSH
t_LDAC
t_DS
t_DH
t_LDS
t_LDH
Clock duration, high
Clock duration, low
CS to clock setup
Clock to CS hold
Load DAC pulse duration
Data setup
Data hold
Load setup
Load hold
MIN
NOM
MAX
10
10
0
10
20
10
10
5
25
(1) All input control signals are specified with t_R = t_F = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
7.7 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
INTERFACE TIMING
t_PD
Clock to SDO propagation delay
MIN
TYP
MAX
2
20
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT
ns
6
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