DAC8812 Datasheet, PDF (18/29 Pages) Texas Instruments – Dual, Serial Input 16-Bit Multiplying Digital-to-Analog Converter

DAC8812
SBAS349D – AUGUST 2005 – REVISED JANUARY 2016
9 Application and Implementation
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NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This design features one channel of the DAC8812 followed by a four-quadrant circuit for multiplying DACs. The
circuit conditions the current output of an MDAC into a symmetrical bipolar voltage. The design uses an op amp
in a transimpedance configuration to convert the MDAC current into a voltage, followed by an additional amplifier
in a summing configuration to apply an offset voltage.
9.2 Typical Application
V_REF
Transimpedance Stage
Gain and Offset Stage
R_G2
R_FB2
REF_IN R_FB
MDAC
I_OUT
+
A₁ ^VDAC
R_G1
+
A₂
V_OUT
Figure 35. Four-Quadrant Multiplying Application Circuit
9.2.1 Design Requirements
Using a multiplying DAC requires a transimpedance stage using an amplifier with minimal input offset voltage.
The tolerance of the external resistors varies depending on the goals of the application, but for optimal
performance with the DAC8812 the tolerance should be 0.1 % for all of the external resistors. The summing
stage amplifier also requires low input-offset voltage and enough slew rate for the output range desired.
9.2.2 Detailed Design Procedure
The first stage of the design converts the current output of the MDAC (I_OUT) to a voltage (V_OUT) using an amplifier
in a transimpedance configuration. A typical MDAC features an on-chip feedback resistor sized appropriately to
match the ratio of the resistor values used in the DAC R-2R ladder. This resistor is available using the input
shown in Figure 35 called R_FB on the MDAC. The MDAC reference and the output of the transimpedance stage
are then connected to the inverting input of the amplifier in the summing stage to produce the output that is
defined by Equation 2.
( ) V_OUT
Code
=
æ
ççè
2_FB2
R _G1
´
V_REF ´ Code
2^bits
ö
÷ø÷
-
æ
çèç
R _FB2
R _G2
´ V_REF
ö
÷ø÷
(2)
9.2.3 Application Curves
Figure 36 shows the output voltage vs code of this design, and Figure 37 shows the output error vs code. Notice
that the error gets worse as the output code increases because the contribution of the DAC gain error increases
with code.
18
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