DAC38RF80_17 Datasheet, PDF (6/155 Pages) Texas Instruments – Dual- or Single-Channel, Single-Ended or Differential-Output, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface and On-Chip PLL

DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
SLASEA3A – DECEMBER 2016 – REVISED FEBRUARY 2017
www.ti.com
NAME
AGND
ALARM
AMUX0
AMUX1
ATEST
CLKTX+
CLKTX-
DACCLK+
DACCLK-
DACCLKSE
DGND
EXTIO
GPI0
GPI1
GPO0
GPO1
IFORCE
RBIAS
RESET
RX0+
RX0-
RX1+
RX1-
RX2+
RX2-
RX3+
RX3-
RX4+
RX4-
RX5+
RX5-
RX6+
RX6-
RX7+
RX7-
SCLK
SDEN
SDIO
SDO
SLEEP
SYNC0+
SYNC0-
SYNC1+
Pin Functions - DAC38RF83, DAC38RF93, DAC38RF85
PIN
I/O
NO.
DESCRIPTION
C11, C12, D11, E11,
F12, J12, K11, L11,
M11, M12
– Analog ground.
CMOS output for ALARM condition. The ALARM output functionality is defined through the config7
K8
O register. Default polarity is active low, but can be changed to active high via config0 alarm_out_pol
control bit.
G3
O Analog test pin for SerDes, Lane 0 to Lane 3. Can be left floating.
F3
O Analog test pin for SerDes, Lane 4 to Lane 7. Can be left floating.
C8
O Analog test pin for DAC, references and PLL. Can be left floating.
A7
O Divided output clock, self-biased, positive terminal.
A6
O Divided output clock, internally biased, negative terminal.
A10
I Device clock, self-biased, positive terminal.
A9
I Device clock, self-biased, negative terminal.
A12
I Single ended device clock optional input. Can be left floating if not used.
A2, B2, C2, D2, D6, E2,
E7, F2, F6, G2, G7, H6,
J7, K2, L2, L3, L4, L5,
M6
- Digital ground.
C10
I/O Requires a 0.1 μF decoupling capacitor to AGND.
K7
- Factory use only. User should GND.
M7
- Factory use only. User should GND.
L7
O Used for CMOS SYNC0\ signal.
L6
O Used for CMOS SYNC1\ signal.
D3
O Test pin for on chip parametrics. Can be left floating.
C9
O
Full-scale output current bias. Change the full-scale output current through DACFS in register DACFS
(8.5.72). Expected to be 3.6 kΩ to GND for 40 mA full scale output.
K9
I
Active low input for chip RESET, which resets all the programming registers to their default state. Internal
pull-up.
J1
I CML SerDes interface lane 0 input, positive
K1
I CML SerDes interface lane 0 input, negative
M1
I CML SerDes interface lane 1 input, positive
L1
I CML SerDes interface lane 1 input, negative
M2
I CML SerDes interface lane 2 input, positive
M3
I CML SerDes interface lane 2 input, negative
M5
I CML SerDes interface lane 3 input, positive
M4
I CML SerDes interface lane 3 input, negative
H1
I CML SerDes interface lane 4 input, positive
G1
I CML SerDes interface lane 4 input, negative
E1
I CML SerDes interface lane 5 input, positive
F1
I CML SerDes interface lane 5 input, negative
D1
I CML SerDes interface lane 6 input, positive
C1
I CML SerDes interface lane 6 input, negative
A1
I CML SerDes interface lane 7 input, positive
B1
I CML SerDes interface lane 7 input, negative
L9
I Serial interface clock. Internal pull-down.
M8
I Active low serial data enable, always an input to the DAC38RFxx. Internal pull-up.
M10
I/O
Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional input 4-pin mode. Internal
pull-down.
M9
O
Uni-directional serial interface data output in 4-pin mode. The SDO pin is tri-stated in 3-pin interface
mode (default).
L8
I Active high asynchronous hardware power-down input. Internal pull-down.
C4
O Synchronization request to transmitter for JESD204B link 0, LVDS positive output.
C3
O Synchronization request to transmitter for JESD204B link 0, LVDS negative output.
C7
O Synchronization request to transmitter for JESD204B link 1, LVDS positive output.
6
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