DAC38RF80_17 Datasheet, PDF (128/155 Pages) Texas Instruments – Dual- or Single-Channel, Single-Ended or Differential-Output, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface and On-Chip PLL

DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
SLASEA3A – DECEMBER 2016 – REVISED FEBRUARY 2017
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8.5.79 Clock Input and PLL Configuration Register (address = 0x31) [reset = 0x0200]
Figure 154. Clock Input and PLL Configuration Register (CLK_PLL_CFG)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 120. Clock Input and PLL Configuration Register (CLK_PLL_CFG)
Bit
15:14
Field
Reserved
13
SEL_EXTCLK_DIFFSE
12
PLL_RESET
11
PLL_NDIVSYNC_ENA
10
PLL_ENA
9
PLL_CP_SLEEP
8
Reserved
7:3 PLL_N_M1
2:0 LOCKDET_ADJ
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
00
0
0
0
0
1
0
00000
000
Description
Reserved
Selects the external differential or single ended clock for
DACCLK.
0 = differential
1 = single ended
When set the M divider; N divider and PFD are held reset
When asserted; the SYSREF input is used to sync the N
dividers of the PLL.
Enables the PLL output as the DAC clock when set; the clock
provided at the DACCLKP/N is used as the PLL reference clock.
When cleared; the PLL is bypassed and the clock provided at
the DACCLKP/N pins is used as the DAC clock
Must be set to '0' for proper PLL operation.
1 = Charge pump is put to sleep and can be driven by external
source through the ATEST pins.
Reserved
Reference clock divider; divide by is N+1
Adjusts the lock detector sensitivity. Upper bit isn't used:
x00 - highest sensitivity x11 - lowest sensitivity
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