CD74HC4017-Q1 Datasheet, PDF (6/14 Pages) Texas Instruments – HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS

CD74HC4017-Q1
HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER
WITH 10 DECODED OUTPUTS
SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
C_L = 50 pF
(see Note A)
LOAD CIRCUIT
High-Level
Pulse
Low-Level
Pulse
50%
t_w
50%
V_CC
50%
0V
V_CC
50%
0V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Reference
Input
Data
Input
50%
10%
t_su
90%
t_r
50%
t_h
90%
V_CC
0V
V_CC
50%
10% _{0 V}
t_f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
Input
In-Phase
Output
Out-of-Phase
Output
50%
t_PLH
50%
10%
t_PHL
90%
90%
t_r
50%
10%
t_f
50%
t_PHL
90%
t_PLH
50%
10%
V_CC
0V
V_OH
50%
10% _VOL
t_f
90% ^VOH
V_OL
t_r
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. C_L includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z_O = 50 Ω, t_r = 6 ns, t_f = 6 ns.
C. For clock inputs, f_max is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. t_PLH and t_PHL are the same as t_pd.
Figure 1. Load Circuit and Voltage Waveforms
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