BQ34210-Q1 Datasheet, PDF (6/19 Pages) Texas Instruments – Automotive 1-Series Cell System-Side CEDV Fuel Gauge for Rarely Discharged Batteries

bq34210-Q1
SLUSCG1 – AUGUST 2017
Integrating ADC (Coulomb Counter) Characteristics (continued)
T_A = –40°C to 85°C; typical values at T_A = 30°C and V_REGIN = 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
V_SRDM
Input differential voltage range of
VSRP–VSRN
±80
t_{SR_CONV} Conversion time
Single conversion
1
Effective Resolution
Single conversion
16
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MAX
UNIT
mV
s
bits
6.11 I²C-Compatible Interface Communication Timing
T_A = –40°C to 85°C; typical values at T_A = 30°C and V_REGIN = 3.6 V (unless otherwise noted) (Force Note1)⁽¹⁾
MIN
NOM
MAX
Standard Mode (100 kHz)
t_d(STA)
Start to first falling edge of SCL
4
t_w(L)
SCL pulse duration (low)
4.7
t_w(H)
SCL pulse duration (high)
4
t_su(STA)
Setup for repeated start
4.7
t_su(DAT)
Data setup time
Host drives SDA
250
t_h(DAT)
Data hold time
Host drives SDA
0
t_su(STOP) Setup time for stop
4
t_(BUF)
Bus free time between stop and start Includes Command Waiting Time
66
t_f
SCL or SDA fall time⁽¹⁾⁽²⁾
300
t_r
SCL or SDA rise time⁽¹⁾⁽²⁾
300
f_SCL
Clock frequency⁽³⁾
100
Fast Mode (400 kHz)
t_d(STA)
Start to first falling edge of SCL
600
t_w(L)
SCL pulse duration (low)
1300
t_w(H)
SCL pulse duration (high)
600
t_su(STA)
Setup for repeated start
600
t_su(DAT)
Data setup time
Host drives SDA
100
t_h(DAT)
Data hold time
Host drives SDA
0
t_su(STOP) Setup time for stop
600
t_(BUF)
Bus free time between stop and start Includes Command Waiting Time
66
t_f
SCL or SDA fall time⁽¹⁾⁽²⁾
300
t_r
SCL or SDA rise time⁽¹⁾⁽²⁾
300
f_SCL
Clock frequency⁽³⁾
400
UNIT
μs
μs
μs
μs
ns
ns
μs
μs
ns
ns
kHz
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
kHz
(1) Specified by design. Not production tested.
(2) Bus capacitance and pull-up resistance impact rise and fall times. View the rise and fall times to assist with debugging.
(3) If the clock frequency (f_SCL) is > 100 kHz, use 1-byte write commands for proper operation. All other transactions types are supported at
400 kHz. (See I²C Interface and I²C Command Waiting Time.)
t_SU(STA)
t_w(H)
t_w(L)
t_f
t_r
t_(BUF)
SCL
SDA
t_d(STA)
t_f
t_r
t_h(DAT)
t_su(DAT)
t_su(STOP)
REPEATED
START
STOP
START
Figure 1. I²C-Compatible Interface Timing Diagrams
6
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