LM3S9B81_15 Datasheet, PDF (56/1271 Pages) Texas Instruments – Stellaris LM3S9B81 Microcontroller

Architectural Overview
1.3.1.4
1.3.1.5
1.3.2
1.3.2.1
1.3.2.2
back-to-back interrupts can be performed without the overhead of state saving and restoration.
Software can set eight priority levels on 7 exceptions (system handlers) and 47 interrupts.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler
for safety critical applications
■ Dynamically reprioritizable interrupts
■ Exceptional interrupt handling via hardware implementation of required register manipulations
System Control Block (SCB) (see page 119)
The SCB provides system implementation information and system control, including configuration,
control, and reporting of system exceptions.
Memory Protection Unit (MPU) (see page 119)
The MPU supports the standard ARM7 Protected Memory System Architecture (PMSA) model. The
MPU provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
On-Chip Memory
The LM3S9B81 microcontroller is integrated with the following set of on-chip memory and features:
■ 96 KB single-cycle SRAM
■ 256 KB single-cycle Flash memory up to 50 MHz; a prefetch buffer improves performance above
50 MHz
■ Internal ROM loaded with StellarisWare software:
– Stellaris Peripheral Driver Library
– Stellaris Boot Loader
– Advanced Encryption Standard (AES) cryptography tables
– Cyclic Redundancy Check (CRC) error detection functionality
SRAM (see page 297)
The LM3S9B81 microcontroller provides 96 KB of single-cycle on-chip SRAM. The internal SRAM
of the Stellaris devices is located at offset 0x2000.0000 of the device memory map.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced
bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Data can be transferred to and from the SRAM using the Micro Direct Memory Access Controller
(µDMA).
Flash Memory (see page 299)
The LM3S9B81 microcontroller provides 256 KB of single-cycle on-chip Flash memory (above 50
MHz, the Flash memory can be accessed in a single cycle as long as the code is linear; branches
incur a one-cycle stall). The Flash memory is organized as a set of 1-KB blocks that can be
individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s.
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July 03, 2014
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