LM3S9B81_15 Datasheet, PDF (471/1271 Pages) Texas Instruments – Stellaris LM3S9B81 Microcontroller

Stellaris^® LM3S9B81 Microcontroller
expected to be returned on the next cycle (when RD is not asserted). If no address is used, then
RD is asserted on the first cycle and data is captured on the second cycle (when RD is not
asserted), allowing more setup time for data.
For writes, the output may be in one or two cycles. In the two-cycle case, the address (if any) is
emitted on the first cycle with the WR strobe and the data is emitted on the second cycle (with
WR not asserted). Although split address and write data phases are not normally needed for
logic reasons, it may be useful to make read and write timings match. If 2-cycle reads or writes
are used, the RW bit is automatically set.
■ Address may be emitted (controlled by the ASIZE field in the EPIGPCFG register). The address
may be up to 4 bits (16 possible values), up to 12 bits (4096 possible values), or up to 20 bits
(1 M possible values). Size of address limits size of data, for example, 4 bits of address support
up to 24 bits data. 4-bit address uses EPI0S[27:24]; 12-bit address uses EPI0S[27:16];
20-bit address uses EPI0S[27:8]. The address signals may be used by the external peripheral
as an address, code (command), or for other unrelated uses (such as a chip enable). If the
chosen address/data combination does not use all of the EPI signals, the unused pins can be
used as GPIOs or for other functions. For example, when using a 4-bit address with an 8-bit
data, the pins assigned to EPIS0[23:8] can be assigned to other functions.
■ Data may be 8 bits, 16 bits, 24 bits, or 32 bits (controlled by the DSIZE field in the EPIGPCFG
register). 32-bit data cannot be used with address or EPI clock or any other signal. 24-bit data
can only be used with 4-bit address or no address. 32-bit data requires that either the WR2CYC
bit or the RD2CYC bit in the EPIGPCFG register is set.
■ Memory can be used more efficiently by using the Word Access Mode. By default, the EPI
controller uses data bits [7:0] when the DSIZE field in the EPIGPCFG register is 0x0; data bits
[15:0] when the DSIZE field is 0x1; data bits [23:0] when the DSIZE field is 0x2; and data bits
[31:0] when the DSIZE field is 0x3. When the WORD bit in the EPIGPCFG2 register is set, the
EPI controller automatically routes bytes of data onto the correct byte lanes such that data can
be stored in bits [31:8] for DSIZE=0x0 and bits [31:16] for DSIZE=0x1.
■ When using the EPI controller as a GPIO interface, writes are FIFOed (up to 4 can be held at
any time), and up to 32 pins are changed using the EPIBAUD clock rate specified by COUNT0.
As a result, output pin control can be very precisely controlled as a function of time. By contrast,
when writing to normal GPIOs, writes can only occur 8-bits at a time and take up to two clock
cycles to complete. In addition, the write itself may be further delayed by the bus due to μDMA
or draining of a previous write. With both GPIO and the EPI controller, reads may be performed
directly, in which case the current pin states are read back. With the EPI controller, the
non-blocking interface may also be used to perform reads based on a fixed time rule via the
EPIBAUD clock rate.
Table 9-7 on page 471 shows how the EPI0S[31:0] signals function while in General-Purpose
mode. Notice that the address connections vary depending on the data-width restrictions of the
external peripheral.
Table 9-7. EPI General Purpose Signal Connections
EPI Signal
EPI0S0
EPI0S1
EPI0S2
General-Purpose
Signal (D8, A20)
D0
D1
D2
General- Purpose
Signal (D16, A12)
D0
D1
D2
General- Purpose
Signal (D24, A4)
D0
D1
D2
General- Purpose
Signal (D32)
D0
D1
D2
July 03, 2014
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