TNETX3150 Datasheet, PDF (55/113 Pages) Texas Instruments – ThunderSWITCHE 15-PORT 10-/100-MBIT/S ETHERNETE SWITCH

TNETX3150/TNETX3150A
ThunderSWITCH^™ 15-PORT 10-/100-MBIT/S ETHERNET^™ SWITCH
SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997
port N RX overrun and collision statistics at 0x8*N + 0x8780 through 0x8*N + 0x87FF
(N = port number in hex)
+7
+6
+5
+4
+3
+2
+1
+0
RX overrun port 00
Collision port 00
RX overrun port 01
Collision port 01
RX overrun port 02
Collision port 02
RX overrun port 03
Collision port 03
RX overrun port 04
Collision port 04
RX overrun port 05
Collision port 05
RX overrun port 06
Collision port 06
RX overrun port 07
Collision port 07
RX overrun port 08
Collision port 08
RX overrun port 09
Collision port 09
RX overrun port 10
Collision port 10
RX overrun port 11
Collision port 11
RX overrun port 12
Collision port 12
RX overrun port 13
Collision port 13
RX overrun port 14
Collision port 14
Reserved
Reserved
ADDRESS
0x8780 +0x00–0x07
0x8780 +0x08–0x0F
0x8780 +0x10–0x17
0x8780 +0x18–0x1F
0x8780 +0x20–0x27
0x8780 +0x28–0x2F
0x8780 +0x30–0x37
0x8780 +0x38–0x3F
0x8780 +0x40–0x47
0x8780 +0x48–0x4F
0x8780 +0x50–0x57
0x8780 +0x58–0x5F
0x8780 +0x60–0x67
0x8780 +0x68–0x6F
0x8780 +0x70–0x77
0x8780 +0x78–0x7F
When accessing the statistics values from the DIO port, it is necessary to perform four 1-byte DIO reads to obtain
the full 32-bit counter. To prevent the chance of the counter being updated while reading the four bytes, the user
should access the low byte first, followed by the upper three bytes. On reading the low byte, the counter statistic
value is transferred to a 32-bit holding register before being placed on the DIO bus. The register is updated only
when reading the low byte of the counter statistic. When the statistics values are accessed in this way, the user
does not see spurious updates.
The statistics, RX overrun, and collision registers are cleared only during a reset or when bit 4 (CLRSTS) of the
system control register at 0x00C3 is set. When the registers roll over, a roll-over indication is not given.
transmit queue (TXQ) structures address map at 0x8*N + 0x8800 through 0x8*N + 0x8807
(N = port number in hex)
+7
+6
+5
Transmit queue 0 head
Transmit queue 1 head
Transmit queue 2 head
Transmit queue 3 head
Transmit queue 4 head
Transmit queue 5 head
Transmit queue 6 head
Transmit queue 7 head
Transmit queue 8 head
Transmit queue 9 head
Transmit queue 10 head
Transmit queue 11 head
Transmit queue 12 head
Transmit queue 13 head
Transmit queue 14 head
+4
+3
+2
Transmit queue 0 tail
Transmit queue 1 tail
Transmit queue 2 tail
Transmit queue 3 tail
Transmit queue 4 tail
Transmit queue 5 tail
Transmit queue 6 tail
Transmit queue 7 tail
Transmit queue 8 tail
Transmit queue 9 tail
Transmit queue 10 tail
Transmit queue 11 tail
Transmit queue 12 tail
Transmit queue 13 tail
Transmit queue 14 tail
Reserved
+1
+0
Transmit queue 0 length
Transmit queue 1 length
Transmit queue 2 length
Transmit queue 3 length
Transmit queue 4 length
Transmit queue 5 length
Transmit queue 6 length
Transmit queue 7 length
Transmit queue 8 length
Transmit queue 9 length
Transmit queue 10 length
Transmit queue 11 length
Transmit queue 12 length
Transmit queue 13 length
Transmit queue 14 length
ADDRESS
0x8800–0x8807
0x8808–0x880F
0x8810–0x8817
0x8818–0x881F
0x8820–0x8827
0x8828–0x882F
0x8830–0x8837
0x8838–0x883F
0x8840–0x8847
0x8848–0x884F
0x8850–0x8857
0x8858–0x885F
0x8860–0x8867
0x8868–0x886F
0x8870–0x8877
0x8878–0x887F
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