TNETX3150 Datasheet, PDF (51/113 Pages) Texas Instruments – ThunderSWITCHE 15-PORT 10-/100-MBIT/S ETHERNETE SWITCH

TNETX3150/TNETX3150A
ThunderSWITCH^™ 15-PORT 10-/100-MBIT/S ETHERNET^™ SWITCH
DRAM flag register at 0x00D8
7
6
DRAMACT
5
Reserved
SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997
BIT
4
3
2
1
0
DRAMFLAG
BIT
NAME
FUNCTION
DRAM test access. DRAMACT contains the status of a DRAM test access READ or WRITE. When this
7
DRAMACT
activity bit is high, the DRAM access is being performed. When this bit is low, the DRAM access has
completed. After a DRAM test access buffer is read, the user should detect a falling edge on this bit before
proceeding to use the accessed data.
6–4
Reserved
Reserved
3–0
DRAMFLAG
DRAM flag field. DRAMFLAG holds a value that maps to the flag field of a DRAM buffer when accessed in
DRAM test-access mode.
DRAM addr register at 0x00D9–0x00DB
BIT
23
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W
DRAMADDRESS
BIT
23
22–0
NAME
R/W
DRAMADDRESS
FUNCTION
DRAM test access read/write. R/W determines whether the contents of channel 0’s FIFO, DRAM data, and
DRAMFLAG are read from DRAM or written to DRAM. When high, the write operation is performed. When
low, a read operation is performed.
DRAM starting word address. DRAMADDRESS is a 23-bit DRAM address marking the starting word
location for a DRAM test access buffer operation.
The DRAM address space (as used in this register) is not flat. It is partitioned in the following manner:
BIT
22
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
DX02
RAS
DX02
CAS
DX01
RAS
DX01
CAS
DX00
RAS
DX00
CAS
Row address (8 bits)
Column address (8 bits)
BIT
22
21
20
19
18
17
16
15–8
7–0
NAME
Reserved
DX02
DX02
DX01
DX01
DX00
DX00
RAS
CAS
FUNCTION
Extended address bit 2 (RAS)
Extended address bit 2 (CAS)
Extended address bit 1 (RAS)
Extended address bit 1 (CAS)
Extended address bit 0 (RAS)
Extended address bit 0 (CAS)
Row address for DRAM (most-significant bit = bit 15)
Column address for DRAM (most-significant bit = bit 7)
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