ADS58B19IRGZT Datasheet, PDF (55/69 Pages) Texas Instruments – 11-Bit, 200MSPS/9-Bit, 250MSPS, Ultralow-Power ADCs with Analog Buffer

ADS58B18
ADS58B19
www.ti.com
SBAS487D – NOVEMBER 2009 – REVISED JANUARY 2011
CLKOUTP
CLKOUTM
D0_P,
D0_M
0
D4
0
D4
D1_D2_P,
D1_D2_M
D0
D5
D0
D5
D3_D4_P,
D3_D4_M
D1
D6
D1
D6
D5_D6_P,
D5_D6_M
D2
D7
D2
D7
D7_D8_P,
D7_D8_M
D3
D8
D3
D8
Sample N
Sample N + 1
Figure 71. ADS58B19 Byte-Wise Sequence (Only with DDR LVDS Interface)
LVDS Output Data and Clock Buffers
The equivalent circuit of each LVDS output buffer is shown in Figure 72. After reset, the buffer presents an
output impedance of 100Ω to match with the external 100Ω termination.
Additionally, a mode exists to double the strength of the LVDS buffer to support 50Ω differential termination. This
mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100Ω
termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH
register bits for data and output clock buffers, respectively.
The buffer output impedance behaves in the same way as a source-side series termination. By absorbing
reflections from the receiver end, it helps to improve signal integrity.
V_DIFF
High
1.1V
V_DIFF
Low
Low
High
OUTP
OUTM
External
100W Load
R_OUT
Figure 72. LVDS Buffer Equivalent Circuit
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