ADC08DL500_15 Datasheet, PDF (53/57 Pages) Texas Instruments – Low Power, 8-Bit, Dual 500 MSPS A/D Converter

ADC08DL500
www.ti.com
SNAS495C – MARCH 2011 – REVISED MARCH 2011
Driving the inputs (analog or digital) beyond the power supply rails. For device reliability, no input should go
more than 150 mV below the ground pins or 150 mV above the supply pins. Exceeding these limits on even a
transient basis may not only cause faulty or erratic operation, but may impair device reliability. It is not
uncommon for high speed digital circuits to exhibit undershoot that goes more than a volt below ground.
Controlling the impedance of high speed lines and terminating these lines in their characteristic impedance
should control overshoot.
Care should be taken not to overdrive the inputs of the ADC08DL500. Such practice may lead to conversion
inaccuracies and even to device damage.
Incorrect analog input common mode voltage in the d.c. coupled mode. As discussed in The Analog Inputs
and THE ANALOG INPUT, the Input common mode voltage must remain within 50 mV of the V_CMO output ,
which has a variability with temperature that must also be tracked. Distortion performance will be degraded if the
input common mode voltage is more than 50 mV from V_CMO .
Using an inadequate amplifier to drive the analog input. Use care when choosing a high frequency amplifier
to drive the ADC08DL500 as many high speed amplifiers will have higher distortion than will the ADC08DL500,
resulting in overall system performance degradation.
Driving the V_BG pin to change the reference voltage. As mentioned in THE REFERENCE VOLTAGE, the
reference voltage is intended to be fixed by FSR pin or Full-Scale Voltage Adjust register settings. Over driving
this pin will not change the full scale value, but can otherwise upset operation.
Driving the clock input with an excessively high level signal. The ADC input clock level should not exceed
the level described in the Operating Ratings Table or the input offset could change.
Inadequate input clock levels. As described in 2.3 THE CLOCK INPUTS, insufficient input clock levels can
result in poor performance. Excessive input clock levels could result in the introduction of an input offset.
Using a clock source with excessive jitter, using an excessively long input clock signal trace, or having
other signals coupled to the input clock signal trace. This will cause the sampling interval to vary, causing
excessive output noise and a reduction in SNR performance.
Failure to provide adequate heat removal. As described in Thermal Management, it is important to provide
adequate heat removal to ensure device reliability. This can be done either with adequate air flow or the use of a
simple heat sink built into the board.
Copyright © 2011, Texas Instruments Incorporated
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