TMS320C6424ZDU7 Datasheet, PDF (52/247 Pages) Texas Instruments – TMS320C6424 Fixed-Point Digital Signal Processor

TMS320C6424
SPRS347D – MARCH 2007 – REVISED DECEMBER 2009
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Table 2-20. Multichannel Buffered Serial Port 0 and Multichannel Buffered Serial Port 1 (McBSP0 and
McBSP1) Terminal Functions
SIGNAL
NAME
ZWT
NO.
ZDU
NO.
TYPE ⁽¹⁾
OTHER ^{(2) (3)}
DESCRIPTION
Multichannel Buffered Serial Port 0 (McBSP0)
For more details on pin multiplexing, see Section 3.7, Multiplexed Pin Configurations.
CLKS0/TOUT0L/
GP[97]
J4
L3
I/O/Z
ACLKR0/CLKX0/
GP[99]
H1
J1
I/O/Z
AHCLKR0/CLKR0/
GP[101]
J2
K1
I/O/Z
AXR0[2]/FSX0/
GP[103]
H3
J2
I/O/Z
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
This pin is multiplexed between McBSP0, Timer0, and GPIO.
For McBSP0, it is McBSP0 external clock source (I).
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 transmit clock CLKX0 (I/O/Z).
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 receive clock CLKR0 (I/O/Z).
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 transmit frame synchronization FSX0
(I/O/Z).
AXR0[3]/FSR0/
GP[102]
G4
J3
I/O/Z
IPD
DV_DD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 receive frame synchronization FSR0
(I/O/Z).
AXR0[1]/DX0/
GP[104]
J3
K2
I/O/Z
IPD
DV_DD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 data transmit output DX0 (O/Z).
AFSR0/DR0/
GP[100]
H4
K3
I/O/Z
IPD
DV_DD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 data receive input DR0 (I).
Multichannel Buffered Serial Port 1 (McBSP1)
For more details on pin multiplexing, see Section 3.7, Multiplexed Pin Configurations.
CLKS1/TINP0L/
GP[98]
K2
L2
I/O/Z
ACLKX0/CLKX1/
GP[106]
F1
G1
I/O/Z
AHCLKX0/CLKR1/
GP[108]
G1
H1
I/O/Z
AMUTEIN0/FSX1/
GP[109]
F2
G3
I/O/Z
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
This pin is multiplexed between McBSP0, Timer0, and GPIO.
For McBSP1, it is McBSP1 external clock source (I).
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McBSP1, it is McBSP1 transmit clock CLKX1 (I/O/Z).
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McBSP1, it is McBSP1 receive clock CLKR1 (I/O/Z).
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McBSP1, it is McBSP1 transmit frame synchronization FSX1
(I/O/Z).
AXR0[0]/FSR1/
GP[105]
H2
H2
I/O/Z
IPD
DV_DD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McBSP1, it is McBSP1 receive frame synchronization FSR1
(I/O/Z).
AFSX0/DX1/
GP[107]
G2
G2
I/O/Z
AMUTE0/DR1/
GP[110]
G3
H3
I/O/Z
IPD
DV_DD33
IPD
DV_DD33
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McBSP1, it is McBSP1 data transmit output DX1 (O/Z).
This pin is multiplexed between McASP0, McBSP1, and GPIO.
For McBSP1, it is McBSP1 data receive input DR1 (I).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1 , Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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