TMS320C6424ZDU7 Datasheet, PDF (151/247 Pages) Texas Instruments – TMS320C6424 Fixed-Point Digital Signal Processor

TMS320C6424
www.ti.com
SPRS347D – MARCH 2007 – REVISED DECEMBER 2009
emulation logic. Power-on Reset is also referred to as a cold reset since the device usually goes through a
power-up cycle. During power-up, the POR pin must be asserted (driven low) until the power supplies
have reached their normal operating conditions. If an external 15–30-MHz oscillator is used on the
MXI/CLKIN pin, the external clock should also be running at the correct frequency prior to de-asserting the
POR pin. Note: a device power-up cycle is not required to initiate a Power-on Reset.
The following sequence must be followed during a Power-on Reset.
1. Wait for the power supplies to reach normal operating conditions while keeping the POR pin asserted
(driven low).
2. Wait for the input clock source to be stable while keeping the POR pin asserted (low).
3. Once the power supplies and the input clock source are stable, the POR pin must remain asserted
(low) for a minimum of 12 MXI cycles.
Within the low period of the POR pin, the following happens:
– The reset signals flow to the entire chip (including the emulation logic), resetting the modules on
chip.
– The PLL Controller clocks start at the frequency of the MXI clock. The clocks are propagated
throughout the chip to reset the chip synchronously. By default, both PLL1 and PLL2 are in reset
and unlocked. The PLL Controllers default to PLL Bypass Mode.
– The RESETOUT pin stays asserted (low), indicating the device is in reset.
4. The POR pin may now be deasserted (driven high).
When the POR pin is deasserted (high), the configuration pin values are latched and the PLL
Controllers changed their system clocks to their default divide-down values. Both PLL Controllers are
still in PLL Bypass Mode. Other device initialization also begins.
5. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles. At the
end of these 10 cycles, the RESETOUT pin is deasserted (driven high).
At this point:
– The I/O pins are controlled by the default peripherals (default peripherals are determined by
PINMUX0 and PINMUX1 registers).
– The clock and reset of each peripheral is determined by the default settings of the Power and Sleep
Controller (PSC).
– The PLL Controllers are operating in PLL Bypass Mode.
– The C64x+ begins executing from DSPBOOTADDR (determined by bootmode selection).
After the reset sequence, the boot sequence begins. For more details on the boot sequence, see the
Using the TMS320C642x Bootloader Application Report (literature number SPRAAK5).
After the boot sequence, follow the software initialization sequence described in Section 3.8, Device
Initialization Sequence After Reset.
6.5.1.1 Usage of POR versus RESET Pins
POR and RESET are independent resets.
If the device needs to go through a power-up cycle, POR (not RESET) must be used to fully reset the
device.
In functional end-system, emulation/debugger logic is typically not needed; therefore, the recommendation
for functional end-system is to use the POR pin for full device reset. If RESET pin is not needed, it can be
pulled inactive (high) via an external pullup resistor.
In a debug system, it is typically desirable to allow the reset of the device without crashing an emulation
session. In this case, the user can use the POR pin to achieve full device reset and use the RESET pin to
achieve a debug reset—which resets the entire device except emulation logic.
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Peripheral Information and Electrical Specifications 151
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