PCI2040_06 Datasheet, PDF (51/78 Pages) Texas Instruments – PCI2040 PCI-DSP Bridge Controller

4.32 HPI CSR I/O Base Address Register
The PCI2040 supports the index/data scheme of accessing the HPI CSR registers. An address written to this register
is the address for the index register and the address + 1 is the data address. The base address can be mapped
anywhere in 32-bit I/O space on a word boundary except at address 0x0000; hence, bit 0 is read-only, returning 0
when read.
The HPI CSR I/O base address is only meaningful when a nonzero value is written into this register.
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
HPI CSR I/O base address
Type
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
HPI CSR I/O base address
Type
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
HPI CSR I/O base address
Read-only, Read/Write
58h
0000 0000h
Table 4−17. HPI CSR I/O Base Address Register
BIT FIELD NAME TYPE
DESCRIPTION
31−1 HPICSR_IO_BAR
RW
Available address bits. These bits can be written by the host in order to allow initialization of the base
address at startup.
0
RSVD
R Reserved. Bit 0 returns 0 when read for word alignment.
4.33 HS Capability ID Register
The HS capability ID register identifies the linked list item as the register for CompactPCI hot swap. This register
returns 06h when read which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer
and the value.
Bit
7
6
5
4
3
2
1
0
Name
HS capability ID
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
1
1
0
Register:
Type:
Offset:
Default:
HS capability ID
Read-only
5Ch
06h
4−19