PCI2040_06 Datasheet, PDF (42/78 Pages) Texas Instruments – PCI2040 PCI-DSP Bridge Controller

4.15 Subsystem ID Register
The subsystem ID register is used for system identification purposes and may be required for certain operating
systems. This register is read-only or read/write depending on the value of bit 0 (SUBSYSRW) in the miscellaneous
control register (see Section 4.26). When bit 0 (SUBSYSRW) is 0, this register is read/write and when bit 0 is 1, this
register is read-only. This register may be loaded from the serial ROM.
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
Subsystem ID
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Subsystem ID
Read-only
2Eh
0000h
4.16 Capability Pointer Register
The capability pointer register provides a pointer into the PCI configuration header where the PCI power management
block resides.
Bit
7
6
5
4
3
2
1
0
Name
Capability pointer
Type
R
R
R
R
R
R
R
R
Default
0
1
0
1
0
0
0
0
Register:
Type:
Offset:
Default:
Capability pointer
Read-only
34h
50h
4.17 Interrupt Line Register
The interrupt line register is written by the host and indicates to which input of the system interrupt controller the
PCI2040’s interrupt pin is connected.
Bit
7
6
5
4
3
2
1
0
Name
Interrupt line
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
1
1
1
1
1
1
1
1
Register:
Type:
Offset:
Default:
Interrupt line
Read/Write
3Ch
FFh
4−10