CC113L Datasheet, PDF (51/75 Pages) Texas Instruments – Value Line Receiver

Bit Field Name
7:0 SYNC[15:8]
0x04: SYNC1 - Sync Word, High Byte
Reset
211 (0xD3)
R/W Description
R/W 8 MSB of 16-bit sync word
CC113L
Bit Field Name
7:0 SYNC[7:0]
0x05: SYNC0 - Sync Word, Low Byte
Reset
145 (0x91)
R/W Description
R/W 8 LSB of 16-bit sync word
Bit Field Name
7:0 PACKET_LENGTH
0x06: PKTLEN - Packet Length
Reset
255 (0xFF)
R/W Description
R/W Indicates the packet length when fixed packet length mode is enabled.
If variable packet length mode is used, this value indicates the
maximum packet length allowed. This value must be different from 0.
Bit Field Name
7:5
4
3 CRC_AUTOFLUSH
2 APPEND_STATUS
1:0 ADR_CHK[1:0]
0x07: PKTCTRL1 - Packet Automation Control
Reset
0 (000)
0
0
1
0 (00)
R/W Description
R/W Use setting from SmartRF Studio [4]
R0 Not Used.
R/W Enable automatic flush of RX FIFO when CRC is not OK. This requires
that only one packet is in the RX FIFO and that packet length is limited
to the RX FIFO size.
R/W When enabled, two status bytes will be appended to the payload of the
packet. The status bytes contain the RSSI value, as well as CRC OK.
R/W Controls address check configuration of received packages.
Setting Address check configuration
0 (00)
No address check
1 (01)
Address check, no broadcast
2 (10)
Address check and 0 (0x00) broadcast
3 (11)
Address check and 0 (0x00) and 255 (0xFF) broadcast
SWRS108
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