CC113L Datasheet, PDF (38/75 Pages) Texas Instruments – Value Line Receiver

regardless of the MCSM1.RXOFF_MODE
18.6 Timing
18.6.1 Overall State Transition Times
The main radio controller needs to wait in
certain states in order to make sure that the
internal analog/digital parts have settled down
and are ready to operate in the new states. A
number of factors are important for the state
transition times:
setting.
CC113L
The crystal oscillator frequency, f_xosc
The value of the TEST0, TEST1, and
FSCAL3 registers
Table 26 shows timing in crystal clock cycles
for key state transitions.
Description
Transition Time
Transition Time [µs]
IDLE to RX, no calibration 1953/fxosc
75.1
IDLE to RX, with calibration 1953/fxosc + FS calibration Time 799
RX to IDLE, no calibration 2/fxosc
~0.1
RX to IDLE, with calibration 2/fxosc + FS calibration Time
724
Manual calibration
283/fxosc + FS calibration Time 735
Table 26: Overall State Transition Times (Example for 26 MHz crystal oscillator, 250 kBaud data
rate, and TEST0 = 0x0B (maximum calibration time)).
18.6.2 Frequency Synthesizer Calibration
Time
Table 27 summarizes the frequency
synthesizer (FS) calibration times for possible
settings
of
TEST0
and
FSCAL3.CHP_CURR_CAL_EN.
Setting
FSCAL3.CHP_CURR_CAL_EN to 00_b disables
the charge pump calibration stage. TEST0 is
set to the values recommended by
SmartRF Studio software [4]. The possible
values for TEST0 when operating with different
frequency bands are 0x09 and 0x0B. The
SmartRF Studio software [4] always sets
FSCAL3.CHP_CURR_CAL_EN to 10_b.
The calibration time can be reduced from
712/724 µs to 145/157 µs. See Section 25.2
on page 44 for more details.
TEST0
0x09
0x09
0x0B
0x0B
FSCAL3.CHP_CURR_CAL_EN
00b
10b
00b
10b
FS Calibration Time
fxosc = 26 MHz
3764/fxosc = 145 us
18506/fxosc = 712 us
4073/fxosc = 157 us
18815/fxosc = 724 us
FS Calibration Time
fxosc = 27 MHz
3764/fxosc = 139 us
18506/fxosc = 685 us
4073/fxosc = 151 us
18815/fxosc = 697 us
Table 27. Frequency Synthesizer Calibration Times (26/27 MHz crystal)
19 RX FIFO
The CC113L contains a 64-byte RX FIFO for
received data and the SPI interface is used to
read the RX FIFO (see Section 10.5 for more
details). The FIFO controller will detect
overflow in the RX FIFO.
When reading the RX FIFO the MCU must
avoid reading it past its empty value since a
RX FIFO underflow will result in an error in the
data read out of the RX FIFO.
The chip status byte that is available on the
SO pin while transferring the SPI header
contains the fill grade of the RX FIFO
(R/W¯ = 1). Section 10.1 on page 22 contains
more details on this.
SWRS108
Page 38 of 68