CC113L Datasheet, PDF (41/75 Pages) Texas Instruments – Value Line Receiver

CC113L
23 General Purpose / Test Output Control Pins
The three digital output pins GDO0, GDO1,
and GDO2 are general control pins configured
with
IOCFG0.GDO0_CFG,
IOCFG1.GDO1_CFG, and IOCFG2.GDO2_CFG
respectively. Table 29 shows the different
signals that can be monitored on the GDO
pins. These signals can be used as inputs to
the MCU.
GDO1 is the same pin as the SO pin on the
SPI interface, thus the output programmed on
this pin will only be valid when CSn is high.
The default value for GDO1 is 3-stated which
is useful when the SPI interface is shared with
other devices.
The default value for GDO0 is a
135 - 141 kHz clock output (XOSC frequency
divided by 192). Since the XOSC is turned on
at power-on-reset, this can be used to clock
the MCU in systems with only one crystal.
When the MCU is up and running, it can
change the clock frequency by writing to
IOCFG0.GDO0_CFG.
If the IOCFGx.GDOx_CFG setting is less than
0x20 and IOCFGx_GDOx_INV is 0 (1), the
GDO0 and GDO2 pins will be hardwired to 0
(1), and the GDO1 pin will be hardwired to 1
(0) in the SLEEP state. These signals will be
hardwired until the CHIP_RDYn signal goes
low.
If the IOCFGx.GDOx_CFG setting is 0x20 or
higher, the GDO pins will work as programmed
also in SLEEP state. As an example, GDO1 is
high impedance in all states if
IOCFG1.GDO1_CFG=0x2E.
SWRS108
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