PCI1520-EP Datasheet, PDF(50/138 Page) Texas Instruments

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PCI1520-EP Datasheet, PDF (50/138 Pages) Texas Instruments – PC Card Controllers

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EEPROM

OFFSET

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

OFFSET

Flag

PCI 04h

PCI 40h

PCI 42h

PCI 44h

PCI 80h

PCI 8Ch

PCI 90h

PCI 91h

PCI 92h

PCI 93h

PCI A2h

ExCA 00h

CB Socket + 0Ch

(function 0)

CB Socket + 0Ch

(function 1)

Table 3â7. Register- and Bit-Loading Map

01h: Load / FFh: do not load

Command register, bits 8, 6â5, 2â0

Note: bits loaded per following:

b8 â b7

b6 â b6

b5 â b5

b2 â b2

b1 â b1

b0 â b0

Subsystem vendor ID bits 7â0 â bits 7â0

Subsystem vendor ID bits 15â8 â bit 7â0

Subsystem ID bits 7â0 â bits 7â0

Subsystem ID bits 15â8 â bits 7â0

PC Card 16-bit I/F legacy-mode base address bits 7â1 â bits 7â1

PC Card 16-bit I/F legacy-mode base address bits 15â8 â bits 7â0

PC Card 16-bit I/F legacy-mode base address bit 23:16 â bit 7:0

PC Card 16-bit I/F legacy-mode base address bits 31â24 â bits 7â0

System control bits 7â0 â bits 7â0

System control bits 15â8 â bits 7â0

System control byte bits 31â24 â bits 7â0

Multifunction routing bits 7â0 â bits 7â0

Multifunction routing bits 15â8 â bits 7â0

Multifunction routing bits 23â16 â bits 7â0

Multifunction routing bits 27â24 â bits 3â0

Retry status bits 7, 6 â bits 7, 6

Card control bits 7, 5 â bits 7, 6

Device control bits 6, 3â0 â bits 6, 3â0

Diagnostic bits 7, 4â0 â bits 7, 4â0

Power management capabilities bit 15 â bit 7

ExCA identification and revision bits 7â0 â bits 7â0

Function 0 socket force event, bit 27 â bit 3

Function 1 socket force event, bit 27 â bit 3

This format must be followed for the PCI1520 to load initializations from a serial EEPROM. All bit fields must be

considered when programming the EEPROM.

The serial EEPROM is addressed at slave address 1010 000b by the PCI1520. All hardware address bits for the

EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample

application circuit (Figure 3â8) assumes the 1010b high-address nibble. The lower three address bits are terminal

inputs to the chip, and the sample application shows these terminal inputs tied to GND.

3.6.4 Accessing Serial-Bus Devices Through Software

The PCI1520 provides a programming mechanism to control serial bus devices through software. The programming

is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3â8 lists the registers used

to program a serial-bus device through software.

3â14

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